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Owing to the intrinsically wide bandgap and high uniformity, amorphous Ga2O3 (a-Ga2O3) has been illustrating a great industrial potential for large-area deep ultraviolet (UV) photosensor arrays. However, a seemingly irreconcilable contradiction between high responsivity and long persistent photoconductivity has hampered the growing pace of such devices. In this work, three-terminal InGaZnO (IGZO)/a-Ga2O3 dual-active-layer (DAL) transistors were developed to realize the ability of a-Ga2O3 as the active layer both in switching and sensing. Benefitting from the introduction of ultrathin IGZO electron reservoir and defect control of a-Ga2O3, the DAL device demonstrates more stable and superior gate-control capability with promising performance including high on/off ratio and field-effect mobility of ∼108 and 8.3 cm2/V⋅s, respectively, as well as a small sub-threshold swing (SS) of 0.36 V/dec. Under 254 nm UV illumination, the DAL device manifests a light-to-dark ratio of ∼108, a responsivity of 4.8 × 103 A W−1, a detectivity of 8 × 1015 Jones, and a UV/visible rejection ratio (R254/R400) of 64. The simultaneous achievement of deep UV photo-detection and transistor's switching performance in a-Ga2O3 material offers excellent potential for the construction of large-area active-matrix UV photosensor arrays with the simple and low-cost fabrication process. [ABSTRACT FROM AUTHOR]

A three‐terminal thin‐film transistor (TFT) architecture is essential for photodetectors to reach a good balance between high responsivity and fast response speed. Bottom‐gate amorphous Ga2O3 (a‐Ga2O3) TFTs are fabricated to boost their UV photodetection properties. During the device fabrication process, a simple chemical‐etching solution with the advantages of easy operation, low cost, and compatibility with traditional lithography process, is developed to selectively etch a‐Ga2O3 films. The a‐Ga2O3 channel etched device on Si manifests an effective suppression of the commonly observed gate leakage current. Meanwhile, a patterned a‐Ga2O3 TFT on quartz shows an excellent n‐type TFT performance with an on/off ratio as high as ≈107. It is further applied as a phototransistor, to diminish the persistent photoconductivity (PPC) effect while keeping a high responsivity (R) as well. Under the 254 nm UV illumination, the a‐Ga2O3 phototransistor demonstrates a high light‐to‐dark ratio of 5 × 107, a high responsivity of 5.67 × 103 A W−1, and a high detectivity of 1.87 × 1015 Jones. Remarkably, the PPC phenomenon in a‐Ga2O3 UV phototransistors is effectively suppressed by applying a positive gate pulse, which greatly shortens the decay time to 5 ms and offers a‐Ga2O3 possible inroads into imaging applications. [ABSTRACT FROM AUTHOR]

Negative drain currents under positive drain-to-gate voltage were found in the OFF-state transfer curves of thin-film transistors (TFTs). A dynamic model was developed, by accounting for capacitances, to interpret the phenomenon. The capacitor discharging during gate voltage sweeping leads to the negative currents. Test conditions and intrinsic device parameters affect the existence of this phenomenon, which is verified by our experimental results of InGaZnO TFTs. [ABSTRACT FROM AUTHOR]

In this paper, we report the fabrication of flexible and transparent InGaZnO thin-film transistors on muscovite mica substrates. The mica substrate is compatible with four-step photolithographic processes as well as high-temperature processes. The field-effect mobility, subthreshold swing, ON/OFF ratio, threshold voltage, and hysteresis voltage are improved after annealing both at 300° C and 400° C in nitrogen. The device demonstrates more stable performance under positive gate bias stress when annealed at 400° C than at 300° C. The electrical performances are stable when exposed to tensile bending cycles up to 10 000 times. The mica with devices shows small optical loss in the visible region, where the average transmittance is as high as 86.75%. [ABSTRACT FROM AUTHOR]

In this paper, we report the fabrication of flexible ZnO thin-film transistors (TFTs) on the 25- $\mu \text{m}$ -thick copper substrate. The Cu substrate compatible with high-temperature processes was deposited by electroplating, which led to a smooth surface. The ZnO layer was deposited at room temperature, and a thermal annealing process was conducted at 300 °C in the air after the fabrication of TFTs. The threshold voltage, hysteresis voltage, and contact resistance are improved after annealing, whereas the mobility, subthreshold swing, and ON/OFF ratio are barely changed. The stabilities of ZnO TFTs are also enhanced, evidenced by the smaller threshold voltage shifts induced by positive and negative gate bias stresses. The field-effect mobility, threshold voltage, and subthreshold swing are stable even when exposed to a mechanical tensile strain up to 1.25% and 10 000 bending cycles. [ABSTRACT FROM AUTHOR]

Integration of oxides with Si opens promising opportunities for novel multifunctional devices and new applications. To optimize the device performances through the hybrid integration, keeping the oxide/Si interface abrupt is critically important and challenging due to the seemingly unavoidable formation of amorphous SiO x or silicide interfacial layers. Here, we report an interface-engineering approach to this issue by molecular beam epitaxy. A BeO thin layer (∼5 nm) was deposited on Si (111) surface using a two-step process of Be deposition and oxidation. The initially formed BeO served as a template for subsequent homo-epitaxial growth of a 10-nm crystalline BeO layer. The well-defined interface between BeO and Si is clearly discerned by high-resolution transmission electron microscopy, implying the role of crystalline BeO as a barrier layer against oxygen atoms' diffusion. High-resolution X-ray photoelectron spectroscopy further confirmed that the combined BeO layers sufficiently protect the Si surface from oxidation. A bottom-gate enhancement-mode thin film transistor was established on a ZnO (130 nm)/BeO (70 nm)/Si architecture, where BeO was functionalized both as a diffusion barrier and as a high- k gate insulator. It indicates that this methodology can be potentially extended to hybrid integration of other technologically important crystalline oxides with Si infrastructures. [ABSTRACT FROM AUTHOR]