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Crystalline or amorphous metal oxides are widely used in various optoelectronic devices as key components, such as transparent conductive electrodes, dielectrics or semiconducting active layers for thin‐film transistor (TFT) backplanes in large‐area displays, photovoltaics, and light‐emitting diodes. Although crystalline inorganic materials demonstrate outstanding optoelectronic performance, owing to their wide bandgaps, large conductivities, and high carrier mobilities, their inherent brittleness makes them vulnerable to mechanical stress, thereby limiting the use of metal‐oxide films in emerging flexible electronic applications. In this study, stress‐diffusive organic–inorganic hybrid superlattice nanostructures are developed to overcome the mechanical limitation of crystalline oxides and to provide high mechanical stability to metal‐oxide semiconductors. In particular, hybrid transparent superlattice electrodes based on crystalline indium–tin oxide exhibit high electrical conductivities of up to 555 S cm–1 (resistance variation < 3%) and effectively reduce the mechanical stress on the inorganic layer (up to 10 000 bending cycles with a radius of 1 mm). Furthermore, to ensure the viability of the hybrid superlattice flexible electronics, all solution‐processed superlattice crystalline indium–gallium‐oxide TFTs are implemented on a thin (≈5 µm) polyimide substrate, providing highly robust and excellent electrical performance (average mobility of 7.6 cm2 V–1 s–1). [ABSTRACT FROM AUTHOR]

Top gate-structured thin-film transistors (TFTs) have a channel inversion region that is directly connected to the doped source/drain area. This stands in contrast with normal bottom gate-structured TFTs that have a channel inversion region on the downward facing side of the silicon layer regardless of the crystallinity. In this experiment, we fabricate a bottom gate TFT with a direct contact junction between the channel inversion layer and the doped source/drain area and subsequently analyze its electrical properties. The leakage current of direct junction structure is 7.4 times higher than indirect junction structure (indirect junction has 2.5 \times 10^-13 A of leakage current and direct junction has 1.85 \times 10^-12 A of leakage current). And we calculate the variation in the specific contact resistance according to differences in the intrinsic silicon thickness in order to confirm the effect that the intrinsic silicon thickness has on the bottom gate direct/indirect contact structure. [ABSTRACT FROM PUBLISHER]

We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 °C for 40 h in order to suppress the glass shrinkage to 0.01 ppm, which suitable for a MILC poly-Si TFT process. The compressive strain that originates from glass shrinkage generally increases the size of the micro-cracks and the vacancies, and as a result, most of the electrical parameters of a bare glass device (such as the on-current, off-current, field-effect mobility, subthreshold slope, and threshold voltage) had a higher level of degradation than those of the device with the compacted glass. The increase in the on-current and the field-effect hole mobility under the compressive strain for poly-Si TFTs showed a similar behavior to that of single-crystalline-silicon (c-Si) TFTs under compressive strain. However, the increase in the off-current was the converse of that of strained c-Si TFT. [ABSTRACT FROM PUBLISHER]

We report on a method to fabricate high-performance bottom-gate poly-Si (BGPS) thin-film transistors (TFTs) with a four-mask process via self-aligned (SA) NiSi2 seed-induced lateral crystallization (SILC). Previously, the BGPS TFT crystallized by SILC was reported to have high electrical performance with a simple process. However, this approach still requires an additional mask for lateral crystallization, making the process more complicated and expensive. In this letter, by using the SA-SILC method, only a few NiSi2 seeds reach the intrinsic Si surface through the side edges of the etch stopper and then crystallize the channel. This SA-SILC enables low metal contamination by a few seeds in the channel, shorter annealing time due to reduced length for SILC, and a simple four-mask process. The SA-SILC BGPS TFTs exhibited a steep subthreshold slope of 0.16 Vdecade ^\mathrm -1 , a high field-effect mobility of 230 cm ^2\textV^-1\texts^-1 , and kink-free output characteristics. [ABSTRACT FROM PUBLISHER]

High-performance poly-Si thin-film transistors (poly-Si TFTs) with metal-induced laterally crystallized (MILC) poly-Si channel and high- k ZrTiO4 (ZTO) gate dielectric are shown for the first time. The MILC poly-Si and ZTO dielectric showed smooth interface ( \sim 1.8 nm) with a low interfacial layer and 4.1 nm of effective-oxide thickness. The electrical performance of MILC poly-Si TFT with ZTO exhibited low threshold voltage of −0.5 V, steep subthreshold slope of 0.25 V/decade, high I\mathrm{{\scriptscriptstyle ON}}/I\mathrm{{\scriptscriptstyle OFF}} of 1.8\times 10^{7} , and high field-effect mobility of 250 cm2/Vs. These characteristics correspond to the best performance of the poly-Si TFTs with high- $k$ gate dielectric reported so far. Moreover, the driving current and field-effect mobility of poly-Si TFT with ZTO gate dielectric were ten times higher than that of poly-Si TFT with deposited-SiO2 gate dielectric. [ABSTRACT FROM AUTHOR]

A compressively stressed polycrystalline-silicon (poly-Si) thin-film transistor (TFT) was successfully demonstrated on a tensile stressed glass substrate. The layer of a-Si:H/bare glass was annealed for 45 h with a sharp annealing and a slow cooled condition in order to form compressive strain on the a-Si:H film. Then, the a-Si:H was crystallized by NiSi2 seed-induced lateral crystallization having (110) preferred texture, and the top-gated TFT was fabricated. The electrical properties were excellent comparing with the strain-free poly-Si TFT, and especially the field-effect mobility increased 9.3 times higher. [ABSTRACT FROM AUTHOR]

We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT’s reliability due to the absent of NiSi2 at the edges and the large effective channel length and width. [ABSTRACT FROM AUTHOR]

An ultrathin channel of poly-Si thin-film transistors with a quasi-lightly doped drain (Q-LDD) structure, which reduces the kink current considerably, have been proposed and fabricated. The doping concentration on the poly-Si channel was adjusted by the different thickness between source–drain and LDD region. The proposed Q-LDD shows advantages of using a thin channel and a thin-gate insulator, comparing with the conventional fabrication process of LDD using a thick oxide side walls. The gate-induced drain leakage currents were successfully suppressed without sacrifice of the ON-current and threshold voltage. Moreover, the kink effect also reduced. [ABSTRACT FROM AUTHOR]

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO 2 as the etch stop interlayer. The Ni trap state density (N t ) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model. [ABSTRACT FROM AUTHOR]