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An accurate and efficient algorithm is presented, which allows deriving the structure function of a discretized 3-D heat conduction problem. In this approach, the partial thermal conductances and capacitances in the structure function are computed in terms of weighted spatial averages of thermal resistivity and volumetric heat capacity. As a result, the exact influence of all materials and geometric details on each part of the structure function is determined. The approach is validated on a state-of-the-art SiGe heterojunction bipolar transistor (HBT) for high-frequency applications. [ABSTRACT FROM AUTHOR]

This paper is aimed at the analysis of the influence of electrothermal and impact-ionization effects on the dc behavior of bipolar cascode amplifiers. A simple physics-based relationship is derived to predict the limit of the safe operating area in the output diagram. Experiments and circuit simulations are performed on amplifiers in GaAs and SiGe technologies to examine and explain the distortion in the dc I-V curves induced by these positive-feedback mechanisms, as well as to predict the temperatures of the individual devices. [ABSTRACT FROM AUTHOR]

This paper presents an improved variant of a dc method to experimentally evaluate the base resistance of a bipolar transistor. The technique relies on a device model associated with a simple parameter optimization methodology, and is suited for modern technologies wherein self-heating and impact-ionization effects play a relevant role. The approach is successfully applied to state-of-the-art SiGe:C heterojunction bipolar transistors for high-frequency applications, although it can in principle be exploited for any bipolar device. The accuracy of the method is verified by numerical and experimental procedures. [ABSTRACT FROM PUBLISHER]

An extensive on-wafer experimental campaign is carried out to determine the thermal resistance dependence on scaling and emitter geometry in state-of-the-art toward-THz silicon–germanium bipolar transistors designed and fabricated within the framework of the European DOTFIVE project. The extraction is performed through a robust procedure which—differently from classic approaches—exploits an accurately calibrated thermometer relating base-emitter voltage to junction temperature. Experimental data are then used to assess the accuracy of scalable thermal resistance laws for advanced transistor models; it was found that at least four parameters are needed to ensure a favorable agreement over wide ranges of emitter widths and lengths. [ABSTRACT FROM PUBLISHER]

This letter presents a geometry scalable approach for the calculation of temperature dependent thermal impedance ( Z\mathbf {TH} ) in trench-isolated heterojunction bipolar transistors. The model is capable of predicting the Z\mathbf {TH} at any desired temperature and bias points. The temperature dependency is derived by discretizing the heat flow region into n number of elementary slices depending on the thermal gradient. Temperature dependent thermal resistances R_{\mathbf {th}} s and capacitances C_{\mathbf {th}}$ s for each of the slices are calculated in a self-consistent manner. Finally, the proposed model is validated with low-frequency measurements at different ambient temperatures ( T_{\mathbf {amb}} ) for different transistor geometries and found to be in good agreement. [ABSTRACT FROM PUBLISHER]

Advanced 3-D thermal simulations of state-of-the-art SiGe:C HBTs are performed, which ensure improved accuracy with respect to conventional approaches. The whole back-end-of-line architecture is modeled so as to account for the cooling effect due to the upward heat flow. Moreover, a nonuniform power density is considered to describe the heat source, and thermal conductivity degradation effects due to germanium, doping profile, and phonon scattering in narrow layers are implemented. The numerical thermal resistances are compared with those experimentally evaluated by means of a robust technique relying on the temperature dependence of the base-emitter voltage. [ABSTRACT FROM AUTHOR]