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DC–DC converter fault diagnosis, executed via neural networks built by exploiting the information deriving from testability analysis, is the subject of this paper. The networks under consideration are complex valued neural networks (CVNNs), whose fundamental feature is the proper treatment of the phase and the information contained in it. In particular, a multilayer neural network based on multi-valued neurons (MLMVN) is considered. In order to effectively design the network, testability analysis is exploited. Two possible ways for executing this analysis on DC–DC converters are proposed, taking into account the single-fault hypothesis. The theoretical foundations and some applicative examples are presented. Computer programs, based on symbolic analysis techniques, are used for both the testability analysis and the neural network training phase. The obtained results are very satisfactory and demonstrate the optimal performances of the method. [ABSTRACT FROM AUTHOR]

Testability analysis is a fundamental prerequisite to any fault location or parameter identification technique (FLPIT) for analog circuits. However, differently from the linear time-invariant field, this topic has been poorly investigated with regard to nonlinear circuits. In this paper, for the first time, to the best of our knowledge, the question is addressed with reference to periodically switched networks with dc stimuli (PSNDSs), a class of inherently nonlinear time-varying circuits that subsumes dc-dc converters as noteworthy members. A rigorous testability measure at both a circuit and a component level is thereby obtained, which provides information as to how many and which components can be unambiguously diagnosed or estimated from time-domain measurements. Consequently, it yields an upper bound, independent of the parameter values and the test instants, to the performance of whatever method actually employed as an FLPIT. This theoretical testability metric has been converted into an efficient computer program for the fully automated testability analysis of PSNDSs presented herein. Such a computer program represents the first practical testability gauge for PSNDSs: it can be employed by both test engineers and circuit designers as a guide to properly selecting injection and measurement points as well as estimating the number of necessary measurement instants, so as to shape their own FLPITs. Several examples are provided for which an in-depth pencil-and-paper testability analysis is contrasted with its automated counterpart provided by the aforementioned software: in particular, popular dc-dc converter topologies are thoroughly analyzed. Comparisons with a previously proposed frequency-domain testability measure are also considered. [ABSTRACT FROM PUBLISHER]

A new procedure for the selection of test frequencies in the parametric fault diagnosis of analog circuits is presented. It is based on the evaluation of algebraic indices, as the condition number and the norm of the inverse, of a sensitivity matrix of the circuit under test. This matrix is obtained starting from the testability analysis of the circuit. A Test Index (T.I.) that permits the selection of the set of frequencies that better leads to locating parametric faults in analog circuits is defined. By exploiting symbolic analysis techniques, a program that implements the proposed procedure has been developed. It yields the requested set of frequencies by means of an optimization procedure based on a genetic algorithm that minimizes the T.I. Examples of the application of the proposed procedure are also included. [ABSTRACT FROM AUTHOR]

In this paper, we present a new method designed to recognize single parametric faults in analog circuits. The technique follows a rigorous approach constituted by three sequential steps: calculating the testability and extracting the ambiguity groups of the circuit under test (CUT); localizing the failure and putting it in the correct fault class (FC) via multi-frequency measurements or simulations; and (optional) estimating the value of the faulty component. The fabrication tolerances of the healthy components are taken into account in every step of the procedure. The work combines machine learning techniques, used for classification and approximation, with testability analysis procedures for analog circuits. [ABSTRACT FROM AUTHOR]

Accurate parameter identification is a patently crucial aspect of system modeling as far as analysis, design, control, maintenance, and fault diagnosis are concerned. In this respect, an essential prerequisite is to establish a priori the solvability degree of the parameter identification problem, which is accomplished by means of testability analysis. The aim of this work is to present a program suitable for fully automated testability analysis of any physical system that can be modeled by an equivalent analog linear time‐invariant electrical circuit. Such a program has been obtained by combining the potentialities of symbolic techniques with the disclosures of a recently proposed theoretical approach to the testability measure concept, able to circumvent the main shortcomings of early methods. An efficient program, characterized by better performances with respect to previous software packages, has been thereby developed, which is herein described from both an algorithmic and a functional viewpoint. It can be advantageously used by the workers interested in system modeling as a guide to devising or refining their own parameter identification strategies. Thoroughly discussed examples of application are also given, which include a complete testability analysis and a novel parameter identification algorithm for electromagnetic harvesters. [ABSTRACT FROM AUTHOR]