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Start Over Descriptor "Test cycle" Topic test vector
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3. Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Author

Badereddine, Nabil, Girard, Patrick, Virazel, Arnaud, Pravossoudovitch, Serge, Landrault, Christian, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Paliouras, Vassilis, editor, Vounckx, Johan, editor, and Verkest, Diederik, editor

Published
2005
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6. Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives

Author

Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault, N. Badereddine, Patrick Girard, Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
Cycles per instruction, Computer science, business.industry, Clock cycle, 05 social sciences, Scan chain, Test vector, 02 engineering and technology, 020202 computer hardware & architecture, Power (physics), Test cycle, Test set, Low-power electronics, 0502 economics and business, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Peak power, Ground bounce, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Heuristics, Telecommunications, business, Test pattern, 050203 business & management
Abstract

International audience; Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Next, we discuss a set of possible solutions to minimize peak power during all test cycles of a scan testing process. These solutions cover power-aware design solutions, scan chain stitching techniques and pattern modification heuristics.

Published
2005

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