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System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC’02 SOC Test Benchmarks show 3.5 and 20 percent reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test scheduling. [ABSTRACT FROM PUBLISHER]

Editor's notes: [ABSTRACT FROM PUBLISHER]

Many system-on-chip (SoC) integrated circuits today contain multiple hierarchy levels for both design and test. Hierarchy imposes constraints on the manner in which tests must be applied to "parent" cores and their "child" cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling is hierarchy oblivious, i.e., these techniques treat all cores in an SoC as if they are at the same level of hierarchy. We first show that the test architecture, consisting of wrappers and TAMs, and the corresponding test schedule designed for nonhierarchical SoCs are not valid for SoCs with hierarchical cores. Next, we present two approaches for efficient testing of SoCs with hierarchical cores. In the first approach, the problem is solved by extending a conventional wrapper design; this approach leaves full flexibility for TAM optimization and test scheduling. The second approach is based on a modified wrapper design for parent cores that operates in two disjoint modes for testing of parent and child cores. This approach has an impact on the test architecture and corresponding schedule. We show how an existing test architecture design algorithm can be adapted for use with both approaches. Experiments with the ITC'02 SoC Test Benchmarks show that the first approach offers lower test application times, while the second approach incurs less area costs. [ABSTRACT FROM AUTHOR]

The article discusses the usage of IEEE Std 1500 in systems on a chip (SoC) testing. It notes that IEEE Std 1500 gives standardized infrastructure that allows modular testing for the digital parts of SoCs wherein the modular testing create total SoC test development. It also present two case application studies that applies the IEEE Std 1500 such as the PNX8550 for digital-video applications designed by Philips Semiconductors Inc., and the STAR TC2 for embedded memories.

Test access mechanisms (TAMs) are an important component of a system-on-chip (SOC) test architecture. TAM optimization is necessary to minimize the SOC testing time. We present a fast, heuristic technique for TAM optimization and demonstrate its scalability for several industrial SOCs. Since the TAM optimization problem is NP-hard, recently proposed methods based on integer linear programming and exhaustive enumeration can be used to design limited test architectures with only a very small number of TAMs in a reasonable amount of time. In this paper, we explore a larger solution-space to design efficient test architectures with more TAMs. We show that the SOC testing times obtained using the new heuristic algorithm are comparable to or lower than the testing times obtained using enumeration. Moreover, significant reduction can be obtained in the CPU time compared to enumeration. [ABSTRACT FROM AUTHOR]