Search

A comprehensive physical model is established to understand the device operation and optimization strategy of the ferroelectric tunnel junction (FTJ). This model is capable of simulating write (switching polarity), read [tunnel electroresistance (TER)], and ac transient operations with a good agreement with experiments. The strategy of optimizing the thickness of the ferroelectric layer and nonpolar interfacial layer is discussed for enlarging TER ratio. We also discussed the possible misinterpretation of the measured TER ratio according to our model. [ABSTRACT FROM AUTHOR]

A device–circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO2 RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized. [ABSTRACT FROM PUBLISHER]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

This letter proposes a novel high bit density nonvolatile memory using a logic compatible flexible amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) structure fabricated at low temperature. Before electrical forming, the a-IGZO TFT exhibits excellent transistor performance, including an ON/OFF current ratio of 8.8\times 10^6, a steep subthreshold slope of 0.14 V/decade, a threshold voltage of 0.55 V, and a maximum field-effect mobility of 2 cm^2/Vs. After electrical forming, a three-bit-per-cell resistive switching memory is realized using localized multilevel resistance states at the drain and source bits. Combining dual functionalities to achieve low-cost integration and excellent device characteristics at bending states, the proposed device is promising for future system-on-plastic applications. [ABSTRACT FROM AUTHOR]

This letter proposes a novel technique for predicting with high confidence the disturbance of the resistive-switching random access memory (RRAM) RESET state based on ramped voltage stress. The technique yields statistical distributions and voltage acceleration parameters equivalent to those of a conventional constant voltage method. Several ramp rates and acceleration models were validated for the accuracy regarding conversion between the two methods. The proposed method not only reduces the time and cost of reliability analysis but also provides a quantitative link between disturbance properties and the widely available RRAM data measured by a linear voltage ramp. Additionally, the non-Poisson area scaling supports the localized filament model. [ABSTRACT FROM AUTHOR]

A novel two-bit-per-cell embedded nonvolatile memory (NVM) device requiring no additional mask and process modification in a logic technology has been proposed using a low-temperature poly-Si thin-film transistor with a \HfO2/\Ni gate stack. The feature of two-bit-per-cell is realized by independent localized resistive switching (RS) at the drain and source bits, respectively, and enables increased bit density over the present single-poly NVM for low-cost embedded applications. Furthermore, minimal degradation of the transistor characteristics after RS allows interchangeable logic/memory operations in an identical device. [ABSTRACT FROM AUTHOR]

A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple \Ni/TiO2/\Ni metal–insulator–metal structure. The highly nonlinear current–voltage characteristics are realized by the Schottky emission over the \Ni/TiO2 barriers. The series connection with an \HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector–one resistor (1S1R) cell structure for high-density crossbar array applications. [ABSTRACT FROM AUTHOR]