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This paper presents a single-inductor triple-source quad-mode (SITSQM) energy-harvesting interface in a 0.18- $\mu \text{m}$ CMOS process. The proposed reversely polarized energy recycling (RPER) technique improves not only the conversion efficiency at low input voltage but also the system’s output power range. The interface employs the buck–boost topology to convert energy from photovoltaic (PV) cells and a thermoelectric generator (TEG) to a regulated 1.2-V output. The proposed converter features four different operating modes, namely, harvesting, recycling, storing, and backup. The operating mode is automatically selected according to the input and load conditions using the automatic source selection mechanism. The experimental results demonstrate 25.3% efficiency improvement and 10 $\times $ output power range extension from the proposed RPER technique. The proposed SITSQM converter automatically manages three harvesting sources with 82.1% peak conversion efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a compact and fully integrated switched-capacitor voltage doubler for voltage boosting in photovoltaic-powered implantable devices. Gate-voltage boosting, nonoverlapping, and interleaving techniques are adopted to enhance the driving capability of the voltage doubler at low supply voltage with high efficiency. A dual-mode three-dimensional (3-D) digital control circuit is proposed to regulate the output voltage under the load current variation. The 3-D control on the number of active converter cells, operation frequency, and on-resistance enable fine output voltage regulation over a wide load current range without extensive device segmentation, thereby reducing the routing complexity and the associated parasitic losses. Other advantages are that the switching loss can be proportionally scaled with the load current for high power efficiency and the periodic charge transfer to the output can keep small for small voltage ripple. Pulse-skipping modulation is employed to allow the converter to operate under ultra-light load. The proposed voltage doubler is designed and implemented using 0.18 μm-CMOS process. The measurement results demonstrate that the proposed converter can generate a voltage of 0.9 V from an input of 0.6 V, with a power efficiency of more than 60% within the output current range of 30–440 μA. The peak efficiency is 73% and the active area is 0.33 mm2. These measurement results suggest that the proposed voltage doubler is suitable for voltage boosting at low voltage under the limited availability of power and area. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-mode digital buck converter with an automatic mode-select feature in a 0.18- $\mu \text{m}$ CMOS for self-powered Internet-of-Things applications. The proposed converter combines the digital pulsewidth modulation and the proposed predetermined pulse-frequency modulation (PPFM) techniques to achieve both a high conversion efficiency and a wide output power range. The proposed PPFM technique calculates the appropriate OFF time of the power transistor in advance, eliminating the additional power budget requirement of the conventional zero-crossing detection circuit. From the results, it can be seen that the conversion efficiency improves by 21% under ultralight-load conditions. The available input voltage ($V_{\mathrm {IN}})$ ranges from 0.55 to 1.8 V for a wide variety of energy harvesters, and the output voltage ($V_{\mathrm {OUT}})$ ranges from 0.3 to 0.55 V to power the energy-efficient CMOS digital circuits. The proposed dual-mode digital buck converter achieves a maximum conversion efficiency of 90.5%, with an output power ranging from 25 nW to 10 mW. Owing to the proposed PPFM technique, the converter achieves a power conversion efficiency of more than 80%, with an output power of 200 nW to 10 mW. [ABSTRACT FROM AUTHOR]

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC–DC (SC DC–DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC–DC switches, DC–DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%–86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices. [ABSTRACT FROM PUBLISHER]

This paper presents a low-phase-noise and wide-tuning-range voltage-controlled oscillator (VCO) implemented in a standard 0.18- \mu \textm complementary metal-oxide–semiconductor (CMOS) process with an integrated passive device (IPD) transformer. Even- and odd-mode oscillations of the transformer-based resonator can be achieved by the mode-switching topology, and the oscillations in the two modes result in a wide tuning range of the VCO. Moreover, the IPD-based transformer achieves high-quality ( $Q$ ) factors ( Q >30$ ), which is impractical in standard CMOS-based technologies due to their lossy silicon substrate. The high- Q$ IPD transformer reduces the phase noise of the VCO and, therefore, leads to a superior figure-of-merit (FOM) and FOM including the tuning range ( ). Operating at 0.8 V supply voltage, the VCO consumes 9.2-mW dc power. At this bias condition, the measured phase noise is −124.2 dBc/Hz at 1-MHz offset from the 6.26-GHz oscillation frequency. Furthermore, the VCO exhibits a 65.7% tuning range and the flipped CMOS chip is packaged on the IPD substrate with a footprint area of 4.35 mm2. Compared with previously published CMOS-based VCOs, the presented VCO features excellent performances in phase noise, wide tuning range, FOM, and \mathrm {FOM}_{T} . [ABSTRACT FROM AUTHOR]

A 1-V-input 0.45-V-output switched-capacitor (SC) voltage converter with voltage-reference-free pulse-density modulation (VRF-PDM) is proposed. The all-digital VRF-PDM scheme improves the efficiency from 17% to 73% at 50- \mu\A output current by reducing the pulse density and eliminating the voltage reference circuit. An output voltage trimming by the hot-carrier injection to a comparator and a periodic activation scheme of the SC voltage converter are also proposed to solve the problems attributed to VRF-PDM. The proposed voltage converter is fabricated in 65-nm CMOS and achieves an efficiency value of 73%–86% at 50 \mu\A–10 mA output current range. [ABSTRACT FROM PUBLISHER]