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Threshold voltage shift ($\Delta {V}_{\text{T}}$) under various current stress (CS) conditions need to be quantitatively studied in self-aligned top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Here, we propose a stretched-exponential function (SEF)-based $\Delta {V}_{\text{T}}$ model that can be applied to various combinations of ${V}_{\text{GS}}$ and ${V}_{\text{DS}}$. The proposed model indicates the characteristic electron trapping time constant $\tau _{1}$ is inversely proportional to (${V}_{\text{GS}} - {V}_{\text{T}}$). In contrast, the time constant $\tau _{2}$ is directly proportional to the square root of (${V}_{\text{DS}}+{V}_{\text{bi}}$), presumably due to the local donor creation by a lateral electric field. The proposed model was verified experimentally in various ${V}_{\text{GS}}$ and ${V}_{\text{DS}}$ configurations. Further, it is confirmed that the lateral electric field dominantly influences donor creation near the drain. [ABSTRACT FROM AUTHOR]

In this study, the oxygen flow rate (OFR) dependence of negative bias illumination stress (NBIS) and positive bias stress (PBS) in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices was investigated. Unlike in previous studies, our study simultaneously considered and analyzed the bias stress-induced degradation mechanisms by charge trapping and defect creation. NBIS and PBS instability were measured according to the OFR splits of bottom-gate (BG) IGZO TFTs and the behavior of full subgap range density of states (DOS) was experimentally tracked with especial emphasis on deep-level oxygen vacancy (${V}_{\text {O}}$) peak. It was found that the observed DOS variation was consistent with the ${V}_{\text {O}}$ ionization model during NBIS. In addition, the threshold voltage shift by charge trapping (${\Delta } {V}_{\text {T,CT}}$) and the threshold voltage shift by defect creation, i.e., change of DOS, (${\Delta } {V}_{\text {T,DOS}}$) were separated and extracted through the subthreshold slope decomposition method. After NBIS, the threshold voltage shift (${\Delta } {V}_{\text {T}}$) was composed of a component by charge trapping and a component with the ionization of ${V}_{\text {O}}$. After PBS, ${\Delta } {V}_{\text {T}}$ was dominated by a component arising due to charge trapping. Fitting through the stretched exponential function (SEF) was performed for each separately extracted ${\Delta } {V}_{\text {T}}$ , and the activation energy for each ${\Delta } {V}_{\text {T}}$ was extracted using the inverse Laplace transform method through the extracted ${\Delta } {V}_{\text {T0}}$ , $\tau $ , and $\beta $. Activation energy by charge trapping and DOS was extracted from NBIS and PBS, respectively. As a result of simultaneously considering the two degradation mechanisms, the extracted activation energy was located between the previous values. Experimentally extracted sets of DOS-specific parameters before and after bias stress were applied to technology computer-aided design (TCAD) simulations. Accurate reproduction of TFT current–voltage (${I}$ – ${V}$) curves before and after bias stress and recovery suggests that the methodology and parameter set used in this study are reasonable and potentially useful for a more robust and systematic analysis of the bias stress-induced instability in a-IGZO BG TFTs. [ABSTRACT FROM AUTHOR]

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under the threshold-voltage $({V}_{T})$ compensated pixel scheme in the backplane of organic light-emitting diode displays and compared with that under a constant-PBS scheme. Based on the investigation, which combines the extraction of density of states, the decomposition of ${V}_{T}$ shift ($\Delta {V}_{T}$), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under the ${V}_{T}$ -compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22− + $2 {e}^{-} \to$ O2− + O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeable $\Delta {V}_{T}$ with an increase in PBS time, our results suggest that the $\Delta {V}_{T}$ should be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment of ${V}_{T}$ -compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test. [ABSTRACT FROM AUTHOR]

We propose an experimental method to decompose the positive gate-bias stress (PBS)-induced threshold voltage shift ( \Delta V\mathsf {th}) of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) into the contributions of distinct degradation mechanisms. Top-gate self-aligned coplanar structure TFTs are used for this letter. Stress-time-divided measurements, which combine the subgap density-of-states (DOS) extraction and the analysis on recovery characteristics, are performed to separate the \Delta V\mathsf {th} components. Change in excess oxygen ( \textO\mathsf {ex}) -related DOS is clearly observed, and \Delta V\mathsf {th} by PBS is quantitatively decomposed into the contributions of the active \textO\mathsf {ex} , and the deep and shallow gate insulator traps. The quantitative decomposition of PBS-induced \Delta V\mathsf {th} provides physical insight and key guidelines for PBS stability optimization of a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

Thin-film transistors using In–Ga–Zn–O (IGZO) semiconductors were evaluated under positive bias stress with different gate and drain voltages ( V\textrm {GS} and V\textrm {DS} , respectively). The transfer characteristics with respect to stress time were examined, focusing on the threshold voltage ( VT ) values obtained when the source and drain electrodes are interchanged during readout (forward and reverse V\textrm {DS} sweep). The VT values shift toward either negative or positive values during stress, while transitions from negative to positive shifts are also observed. The negative VT shift under positive bias stress is interpreted to occur by the generation of donor-like states related to ionized oxygen vacancies. On the other hand, positive VT shifts result from the trapping of electrons near the IGZO/gate insulator interface. The transitions from negative to positive VT shift are believed to result from the local electron trapping mechanism that gradually takes over donor-like state creation. From the experimental results and TCAD device simulation, it is suggested that a competition occurs between donor-like state creation and electron trapping. The relative magnitudes of the V\textrm {GS} and V\textrm {DS} fields determine which mechanism dominates, providing an analytical insight for the design of stable devices for driving transistors in AMOLED backplanes. [ABSTRACT FROM AUTHOR]

Hump characteristics of n-channel amorphous indium-gallium–zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage ( VT ) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS ( V\mathrm {GS}=30 , V\mathbf {DS}=30 ; V\mathrm {GD}=V\mathrm {GS}-V\mathrm {DS}=0 V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage ( V\mathrm {Tp} ) and a shorter effective channel length ( L\mathrm {chp}\cong L\mathrm {ov} ) compared with those ( V\mathrm {Tm} and L\mathrm {ch} ) of the main TFT. [ABSTRACT FROM PUBLISHER]

Thin-film transistors using In-Ga–Zn-O (IGZO) semiconductors were evaluated under current stress by applying positive voltages to the gate and drain electrodes. Initially, the transfer characteristics exhibit identical threshold voltages ( VT) when the source and drain electrodes are interchanged during measurement (forward and reverse V\mathrm {DS} sweep). However, as stress time increases, larger shifts in VT are observed under forward V\mathrm {DS} sweep than under reverse V\mathrm {DS} sweep conditions. Subgap states analyses based on the photoresponse of capacitance-voltage ( $C$ – $V$ ) curves suggest that local annihilation of donor-like traps occurs near the drain electrode. Hump-like features are clearly observed in the $C$ – $V$ curves collected between the drain and gate electrodes, while they do not appear in the $C$ – $V$ data obtained between the source and the gate. Based on the above, a local charge trapping model is introduced in order to interpret the device degradation. In this model, the major carrier electrons are trapped more abundantly near the source electrode due to the presence of a Schottky junction between IGZO and the source/drain electrodes. [ABSTRACT FROM AUTHOR]