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The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques. A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies. This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages. The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry. Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation. The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm. A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved. The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure. These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure. SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal. DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code. The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high. Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 3.68 (height of 2mm and diameter of 550μm). Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity. A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation. ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer. Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process. After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane. A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers. This complete procedure could be repeated numerous times to fabricate multilayer electronic devices. This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads. The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways. Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch. A flip-chip bonding force of 0.08 N resulted in a contact resistance of 2.3 Ω at a standoff height of ~80 μm. Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful. Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis. This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality.