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Existing vectorless methods use a statistical approach to estimate the average number of switching events in a digital circuit. While these methods allow one to predict the average power consumption, a critical parameter for many digital designs, they cannot be used to predict the statistical variation in power consumed in each clock cycle, which is necessary to estimate the bounds on power supply noise. A vectorless method is proposed for estimating the variance in the number of switching events across a digital design. This result may be used to estimate variance in power supply noise. The approach was tested on a 5 × 5 adder array. The standard deviation in the total number of switching events can be found within 1% for this design. Including covariance among switching events at different gates was critical. When covariance was ignored, the standard deviation was underestimated by nearly 84%. The proposed approach allows rapid estimation of a reasonable worst case number of switching events that may occur in a single clock cycle. [ABSTRACT FROM AUTHOR]

Switching of logic gates is often responsible for significant power supply noise. Predicting the jitter resulting from the power supply noise can be critical to analyze the proper operation of high-speed devices. The statistical characteristics of jitter, such as the mean standard deviation of jitter, can be used to place a meaningful bound on the worst-case timing margin and to estimate the bit error rate. While the statistical characteristics of the noise can be found through simulations of many input logic vectors, such simulations require significant computational effort and require methods for choosing suitable data vectors. Vectorless methods allow rapid analysis of switching without using predefined input data and can be used to understand which portions of the logic circuit contribute most to the noise. In this paper, methods using vectorless techniques are presented to predict the mean and standard deviation of the power supply noise on the printed circuit board (PCB), and the mean and standard deviation of the resulting peak-to-peak jitter in a driver on the same PCB. In experiments, the techniques were able to predict the average and standard deviation of the peak power supply noise on the PCB with 2% and 8% error, respectively, and of the peak-to-peak jitter with 21% error, which is sufficient for predicting how a specific logic design might impact jitter, and for proposing means to minimize that impact. [ABSTRACT FROM AUTHOR]