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In this article, we propose a framework for determining approximation levels of approximable memories in a memory hierarchy for executing error resilient applications. The framework aims at optimizing the configuration for employing approximate memories in a computing system. It is based on considering data footprints at different memory hierarchy levels and an expected output quality to determine the amount of approximations at each memory hierarchy level. The problem of finding a suitable memory approximation configuration is performed using a branch-and-bound algorithm considering all possible memory approximation arrangements. The best configuration leading to the lowest power consumption when meeting the expected output quality is selected. The efficacy of the proposed framework for two memory hierarchies with different cache topologies is evaluated by comparing energy consumptions of approximate memories with those of the exact memory units in the memory hierarchy under different output accuracy level targets. For example, with 28 dB as a peak signal to noise ratio (PSNR) constraint, the study, which is performed for four image processing applications, indicates up to 54% and 22% power consumption improvements for the SRAM cache and the DRAM memory, respectively. [ABSTRACT FROM AUTHOR]

In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1V down to 0.5V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. [ABSTRACT FROM AUTHOR]

In this paper, we propose a robust SRAM design which is based on FinFETs. The design is performed by dynamically adjusting the back-gate voltages of pull-up transistors. For the write operation, we use an extra write driver which sets the desired back-gate voltages during this operation. This approach considerably increases the write margin. During the hold state, the back-gates are precharged to the supply voltage using an extra precharge circuit. This decreases the static power. Finally, we use nMOS switches to provide the optimum back-gate voltages during the read state. To minimize the area and power overheads, an instance of the circuitry is used for each column. The performance of the proposed technique is assessed using mixed mode device/circuit simulations for a physical gate length of 22 nm. The results show that the minimum operating voltage for six-sigma read and write yield is about 0.15 V lower than that of the recently proposed structures. In addition, the suggested SRAM shows significantly higher write margin and lower static power compared to the recently proposed structures. The minimum operating voltage of our proposed structure can be lowered down to 0.5 V through some work function tuning to balance the read and write stability. This minimum voltage is 0.1 V lower than the minimum operating voltage of the other structures with similar work function tunings. [ABSTRACT FROM AUTHOR]

In this paper, an optimal approach for the design of 6-T FinFET-based SRAM cells is proposed. The approach considers the statistical distributions of gate length and silicon thickness and their corresponding statistical correlations due to process variations. In this method, a back-gate voltage is used as the optimization knob. With the help of particle swarm optimization (PSO), the back-gate voltages that maximize the yield of the SRAM array against read, write, and access time failures are found. It will be shown that, with this method, a very high yield is achieved. [ABSTRACT FROM AUTHOR]

In this paper, an accurate aging model for Read Static Noise Margin (RSNM) of conventional 6 transistors (6T) FinFET SRAM cell is presented. The model, which is developed based on accurate I - V formulation suitable for FinFET, considers soft oxide breakdown (SBD) as well as bias temperature instability (BTI) effects. The accuracy of the model is verified by comparing its results with those of HSPICE simulations for the 14 nm and 10 nm technologies. The results show the maximum errors of 0.63% and 0.54% for the 14 nm and 10 nm technologies, respectively, when averaged over a wide range of stress times and supply voltages. The model also may be used to accurately predict the cumulative distribution function of the RSNM in the presence of the process variation with a very small error compared to the one obtained from the Monte Carlo approach with a considerably short runtime. [ABSTRACT FROM AUTHOR]

In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on / I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal high write and read margins, the highest I on / I off ratio, a fast write, and ultra-low leakage power in the hold “0” state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from −40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400 mV and 500 mV. The study shows that the proposed cell meets the required cell sigma value (6 σ ) under all conditions. [ABSTRACT FROM AUTHOR]