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Prognostic health monitoring technologies, which can evaluate performance degradation, load history, and degree of fatigue, have the potential to improve the effective maintenance, reliability design methods, and availability under improper use conditions of electronics systems. We propose a method to assess the thermal fatigue life and thermal load history under asymmetric cycles of a power electronics module by using finite element method-based Lagrangian neural networks. We apply this method to an insulated-gate bipolar transistor power module with a temperature history monitoring function. It is shown that this method can estimate the inelastic strain cycles and thermal fatigue life distribution of the solder joints from temperature monitoring history. It is also confirmed that probabilistic load assessment of thermal cyclic load distributions can be conducted using the estimated inelastic strain cycles. It is concluded that the proposed method could be effective for assessing thermal load history and thermal fatigue life estimation in prognostic health monitoring.

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. In the present study, the new method of estimating the crack propagation, called 'damage path simulation', was applied for solder bumps under the mechanical fatigue tests. The new method is based on finite element analysis without geometrical crack model, and on the characteristic damage model assumed for solder. Damage paths from the entire circumference in the vicinity of the interface were simulated, and they were finally combined at the center of bumps. The extension of the damage path showed good agreement with the behavior of crack propagation observed in the mechanical fatigue tests. In the case of solder bumps, the effects of the assessment of the previous damage on the extension rate of the damage path might be critical issue. However, the effects of the assessment of the previous damage were relatively small, in consideration of the large scattering in the results of mechanical fatigue tests. It was confirmed that the number of cycles to the fatal failure of solder bumps can be accurately estimated by the damage path simulation. It was concluded that the estimation of the crack propagation based on the proposed method is satisfactory for engineering purposes.

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined. On the basis of a damage model assumed for solder, the new method called 'damage path simulation' was verified for solder joints in QFP (Quad Flat Package). It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead was also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined. The advantage of the proposed method was especially evident when the fatigue cracks were initiated from two or more regions. The effects of the frequency of thermal cycle were also discussed. It was shown that the frequency of thermal cycle has a noticeable effect on the crack propagation rate. It was concluded that the estimation of the crack propagation in solder joints based on the proposed method is satisfactory for engineering purposes.

Continuing improvements in both capacity and miniaturization of electronic equipment such as solid state drives (SSDs) are spurring demand for high-density packaging of NAND-type flash memory mounted on SSD printed circuit boards. High-density packaging leads to increased fatigue failure risk of solder joints due to the decreased reliability margin for stress. We have developed a failure precursor detection technology based on fatigue failure probability estimation during use. This method estimates the cycles to fatigue failure of an actual circuit by detecting broken connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail earlier than the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. The statistical distribution of the strain range of solder joints can be provided by Monte Carlo simulations based on the finite element method and random load modeling. A feasibility study of the failure probability estimation method is conducted by applying the method to a printed circuit board on which a ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint’s fatigue failure.

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.Copyright © 2013 by ASME