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Wafer-Level Chip Scale Packages (WLCSPs) are becoming commonplace in the industry due to their small form factor. Applications include industrial and automotive which demand high reliability performance. Additionally, WLCSPs may be superior in some implementations to other package options for RF performance in the mmWave spectrum, which is desired for automotive radar application. But board level reliability can be a challenge for some WLCSP package due to CTE mismatch between Si and PCB. Variety of factors including PCB materials, sphere alloys, and board level underfills can influence the board level reliability of WLCSP packages. In this study the industry’s first auto grade 1 capable large WLCSP package. (~ 72 mm2 body size, 18x15 BGA array, 0.5 mm pitch) is presented. Board level underfill application was utilized to achieve automotive grade board level reliability. Underfills are typically selected based on thermomechanical properties of unaged materials. An understanding of the evolution of underfill material properties under thermal aging is important for selecting a stable material capable of meeting the reliability requirements. This study evaluates board level underfills and edge bond materials in the form of stand-alone samples and applied to a large daisy-chain WLCSP. The underfilled daisy-chain WLCSPs and the stand-alone samples are placed in a ‑40/125C air cycling chamber (1 cycle/hour). Glass transition temperature (Tg), elastic modulus (E), and coefficient of thermal expansion (CTE) are measured using Dynamic Mechanical Analysis (DMA) and Thermomechanical Analysis (TMA) on the stand-alone samples at various intervals to monitor the evolution of material properties. Simultaneously, the underfilled daisy chain WLCSPs are monitored electrically using an event detector. The combination of material property measurements and cycles to electrical failure can be used to correlate underfill material properties and WLCSP board-level reliability. The results of this study can provide material property guidance for underfill selection.

In present study, the effects of thermal cycling and vibration on cracking in Sn-3.0Ag-0.5Cu (SAC305) solder bump (interconnection between flip chip and printed circuit board) were studied. The thermal cycling test was set in 2 conditions as “TC180C” and “TC140C” that differed in temperature cycle i.e. 15 °C to 180 °C and 15 °C to 140 °C, respectively. While, the vibration test was also set in 2 conditions as “VB20G”and “VB05G” that differed in vibration acceleration ranges i.e. 20G and 5G respectively. Crack initiation and propagation in SAC305 solder bump were investigated by interrupted tests using scanning electron microscope. Results of the thermal cycling tests indicated that cracks initially developed at the edge of solder bump and subsequently propagated along solder/intermetallic compounds layer interface for TC180C condition. While crack propagated to bulk solder for TC140C. And crack initiation cycle differed between test conditions that were 40 cycles and 60 cycles for TC180C and TC140C, respectively. Crack initiation and propagation were accelerated by temperature range. The lower number of crack initiation cycle for TC180C condition, which was operated under a large temperature range, would be induced by higher thermal strain that could accelerate crack initiation in SAC305 solder bump. Results of the vibration tests showed that crack initiation and propagation were found only under VB20G condition, the number of crack initiation cycle was 12 cycles at X vibration axis. While any crack was not found for VB05G condition. The crack initiation and propagation in the SAC305 solder bump under VB20G condition would be induced by higher mechanical vibration acceleration. Whereas, damage accumulation in the SAC305 solder bump would not be induced by lower mechanical vibration acceleration under VB05G condition.

In this work, we study the Transient Liquid Phase Bonding (TLPB) for flip chip interconnexion using copper pillar and SnAg solder alloy technologies. Cu and SnAg bumps with a size of 90 × 90 µm2 were deposited using electroplating process with a thickness of 20 µm and 15–30 µm, respectively. Two types of Cu were deposited: with or without additives. Before the TLPB process, soldering experiments with or without pre-reflow were carried out at 250 °C in order to insure a good filling of the joint. Afterwards, isothermal holdings up to 4 h were performed in the temperature range between 250 and 350 °C under air atmosphere. Two main aspects of Cu/SnAg system are studied and analyzed: (i) the evolution of morphology, microstructure, and growth kinetics of intermetallics (IMCs) during the TLPB and especially (ii) the formation and growth of gas bubbles within the liquid solder during TLPB process. Destructive (scanning electron microscopy) and non-destructive (X-ray) characterizations are performed to analyze and understand the evolution of microstructure as well as the formation and evolution of cavities within the joint during the TLPB process. Non-destructive X-ray radiography with 5 µm resolution and 3D X-ray tomography analysis with 0.7 µm resolution were conducted for the same joint at different steps of its evolution between its initial state (just after the soldering process: about 3 min at 250 °C) and 4 h at 250 °C in order to follow “in situ” the evolution of volume defects inside the joint and especially the evolution of gas bubbles within the joints.

The present work investigated the effect of Ag additives on the consumption of cathode Cu pad under electromigration in a current-stressed Cu/Sn3.5Ag/Cu flip-chip structure. The consumption rate of a cathode Cu pad in a pure Sn system is faster than that of a cathode Cu pad in a Sn3.5Ag system at 80℃ by a factor of 10. Using the kinetics of the consumption equation, the activation energy in the consumption of a cathode Cu pad was calculated. The activation energy (0.65 eV) of the consumption of a cathode Cu pad in a Cu/Sn3.5Ag/Cu flip-chip structure under electromigration (EM) is slightly greater than that (0.62 eV) of the consumption of a cathode Cu pad in a Cu/Sn/Cu flip-chip structure under EM. The dissolution of Cu flux is discussed, and the possible effect of Ag additives on the consumption rate of a cathode Cu pad under EM is proposed. The Ag additives reduced the deficiency of Cu solubility in a solder matrix near the cathode Cu/solder interface, which is the main factor in the reduction of Cu pad consumption. Moreover, the Ag3Sn phase forming on the cathode Cu6Sn5 interface protects Cu6Sn5 from dissolving into the Sn3.5Ag solder matrix under EM.

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

Purpose This paper focuses on the fluid-structure interaction (FSI) analysis of moisture induced stress for the flip chip ball grid array (FCBGA) package with hydrophobic and hydrophilic materials during the reflow soldering process. The purpose of this paper is to analyze the influence of moisture concentration and FCBGA with hydrophobic material on induced pressure and stress in the package at varies times. Design/methodology/approach The present study analyzed the warpage deformation during the reflow process via visual inspection machine (complied to Joint Electron Device Engineering Council standard) and FSI simulation by using ANSYS/FLUENT package. The direct concentration approach is used to model moisture diffusion and ANSYS is used to predict the Von-Misses stress. Models of Test Vehicle 1 (similar to Xie et al., 2009b) and Test Vehicle 2 (FCBGA package) with the combination of hydrophobic and hydrophilic materials are performed. The simulation for different moisture concentrations with reflows process time has been conducted. Findings The results from the mechanical reliability study indicate that the FSI analysis is found to be in good agreement with the published study and acceptable agreement with the experimental result. The maximum Von-Misses stress induced by the moisture significantly increased on FCBGA with hydrophobic material compared to FCBGA with a hydrophilic material. The presence of hydrophobic material that hinders the moisture desorption process. The analysis also illustrated the moisture could very possibly reside in electronic packaging and developed beyond saturated vapor into superheated vapor or compressed liquid, which exposed electronic packaging to higher stresses. Practical implications The findings provide valuable guidelines and references to engineers and packaging designers during the reflow soldering process in the microelectronics industry. Originality/value Studies on the influence of moisture concentration and hydrophobic material are still limited and studies on FCBGA package warpage under reflow process involving the effect of hydrophobic and hydrophilic materials are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the microelectronics industry.

With the development of the automotive industry, the number of automotive electronic components is growing rapidly. This leads to new requirements for reliability of the automotive electronics. Especially, for difficult operating environments, such as engine compartment of the car, extreme thermal cycles, and long holding time, where prediction of the fatigue life of the component is particularly important. In this study, thermal fatigue life prediction models for two packages are proposed: TSOP over BGA, and flip chip with BGA. The overall deformation of the two packages was analyzed using Moire fringes, and was found to be consistent with simulation results. The reliability of the model was verified by comparing thermal shock results and simulation results. Then, the fatigue life of the component under thermal cycles was predicted using the model. The overall component life of the BGA with flip chip package was 818 cycles. For TSOP over BGA this was 1005 cycles, but the shortest life of the BGA was 725 cycles, which may result in the failure of the entire component. The fatigue life prediction using different models is helpful to assess and optimize components at the early stage of product development.

The demand for miniaturised electronic devices has led to various challenges in microelectronic industries. One of the challenge is the removal of fans in some applications, which has led to increased heat retention, thereby causing overheating. In the assembly of electronic devices, thermal interface materials (TIMs) can be used for bonding the surface between the flip chip and a heat sink base or heat spreader. Lead-free solder (Sn-Ag-Cu) alloys are becoming more popular as TIMs in electronic assembly. Therefore, these lead-free solders could fail during operation at elevated temperatures over a period of time. The reliability of lead-free TIMs is vital in sustaining the life span of an electronic device. Three Sn-Ag-Cu (SAC) solders were considered for this investigation, namely, SAC305, SAC105, and SAC396. An ANSYS design modeller was used in the design and analysis of the microelectronic application investigated. Temperature loads ranging between 100°C and 200°C were applied over a period of time during the simulation of the electronic package. The findings from the research suggested that the SAC305 solder TIMs will outperform SAC105 and SAC396 during operation. This is because SAC305 can accommodate more stress, while the strain rate is low compared to SAC105 and SAC396. In addition, the fatigue life of SAC305 was higher than that of SAC105 and SAC396 in the different temperature ranges investigated. Therefore, SAC305 is recommended as a better thermal interface material compared to SAC105 and SAC396.

Thermal compression bonding (TCB) has been widely used in flip chip bonding processes for three-dimensional integrated packaging. Therefore, studying the TCB process and solder joint structure is significant for improving reliability. In this study, a Ni layer was deposited between the Cu/Sn-3.5Ag solder bumps of upper and lower chips, and TCB process tests were carried out at different bonding temperatures, forces and times. The solder height at the top and bottom of the copper pillar were recorded. Through the establishment of a mathematical analysis model, the relationship between the solder joint height and maximum stress was analyzed theoretically, and the trend of the shear stress and solder joint height was obtained from die shear tests. Then, the solder joint morphology, strength and microstructure composition of the microbumps were observed after aging. Our results showed that the growth rate of intermetallic compounds (IMCs) for Cu/Sn-3.5Ag microbumps with a 25 μm diameter was 2.5 times those with a 100 μm diameter and that the Ni barrier layer prevented the diffusion of Cu in Sn-3.5Ag solder. In addition, the Ni layer improved the strength of the Cu/Sn-3.5Ag joints after aging. Finally, with extended aging time, the fracture site was found to move from the solder region to the Cu6Sn5 layer for the Cu/Sn-3.5Ag samples, while it remained at the Sn-3.5Ag/IMC interface for the Cu/Ni/Sn-3.5Ag samples.

The wettability and growth of intermetallic compounds (IMCs) of stud bump materials Ag, Ag-4Pd, Cu, and Au with Sn-3Ag-0.5Cu (SAC305) solder have been investigated. Stud bumps produced using wire bonding techniques are widely employed in flip chip assembly, especially in 3D integrated circuit packaging. The material of stud bumps is a key factor in the reliability of the bonds. The wettability of IMCs as studied in this study decreased in the order Au > Ag ≈ Ag-4Pd > Cu, indicating that Ag and Ag-alloy bumps were only slightly inferior to those of Au but superior to those of Cu. Moreover, the morphologies and growth behaviors of the IMCs were evaluated by aging at 100°C to 200°C for 100 h to 1000 h. Without the gold embrittlement effect found in Au or the Kirkendall void issue of Cu, IMCs contained mainly Ag3Sn at the interface after long-term aging tests, and thickened IMCs with Ag3Sn and PdSn4 were observed in the case of Ag-4Pd after prolonged aging for 1000 h at 200°C. The growth kinetics of the IMCs in Ag and Ag-4Pd stud bumps with SAC305 solder followed the Arrhenius equation, with activation energies of 56.45 kJ/mol and 57.37 kJ/mol, respectively. The formation mechanisms of the IMCs in Ag and Ag-4Pd stud bumps were found to be diffusion controlled. The results indicated that Ag and Ag-4Pd are better than Au and Cu for application as stud bump materials.

Due to the increased complexity and optimization in microprocessor packaging from 2D to 3D packages, the size of solder joints is being reduced significantly. This trend currently leads to an increased amount of current density across flip-chip solder joints as well as microbumps and causes electromigration-oriented void formation and subsequent failure of the solder joints. It has been observed from literature that solder material undergoes microstructure evolution and subsequent degradation of mechanical properties under isothermal aging conditions. The current study is based on the effects of material property degradation due to thermal aging of flip-chip Sn-Ag-Cu (SAC) solder joints on electromigration-oriented failure. Finite element analysis has been used to analyze the diffusion characteristics of a SAC solder joint under isothermal aging conditions of 100°C for a period of 1–20 days, and electromigration simulation has been performed at two different temperatures of 100°C and 125°C for 100 h at an input current range of 0.01–0.05 A. The effect of intermetallic compound (IMC) layer thickness is analyzed to reveal the impact on electromigration-oriented failure in isothermally 60 days long aged solder bumps. Results have revealed that resistance to electromigration-oriented failure is higher in the case of aged components compared to unaged components along with the increment of time to failure with IMC formation in the SAC solder joint.

This paper investigates the effect of different soldering temperatures on the performance of the flip-chip light-emitting diode (FC-LED) filament during direct soldering. The changes in the intermetallic compound (IMC) interface, push–pull force and chip fracture surface of the chip solder joints under direct soldering temperatures of 220°C, 260°C, and 320°C for the flip-chip LED filament were explored by scanning electron microscopy (SEM). Thereby, the optimal soldering temperature of direct joining in actual production is compared. The results show that when the soldering temperature is 260°C, Cu on the substrate begins to diffuse into the solder and react with the solder in the lower layer. The Sn content is relatively uniform, and the average push–pull force of the chip increases. The fracture occurs from inside the solder. With a soldering temperature of 260°C, it is observed that the interface shear stress of the flip-chip LED chip is the largest, and the mechanical stress and residual stress are the lowest.

The finite element software ANSYS was used to simulate the solder joints in the flip chip, and the stress and strain distribution results of the solder joints are displayed. During the simulation process, the final results of the simulation were not the same when the solder joints of different sizes were used. The simulation results under thermal cycling load show that the area where the maximum stress and strain occur is mostly distributed in the contact area between the solder joint and the copper pillar and at the solder joint. During the entire thermal cycling load process, the area where the maximum change in stress and strain occurs is always at the solder joint, and when the temperature changes, the temperature at the solder joint changes significantly. From the comprehensive analysis, the relevant empirical correction calculation equation is used to calculate and predict the thermal fatigue life of the solder joint. We found that when the diameter of the solder joint is constant, the increase in the height of the weld point will increase its thermal fatigue life; when the height of the weld point is constant, the increase in the diameter of the weld point increases its thermal fatigue life. The effect of height is greater than the effect of diameter.

Stud bumping using a traditional wire bonding process followed by the severing of the wire material from the ball bond has been widely applied in flip chip packages. Traditionally, Au stud bumps were employed because of the physical properties of gold, but the mediocre reliability of Au with Al pads and the cost of gold make this material unfavorable for industrial needs. Copper stud bumps were also considered, but the intrinsic features of Cu, such as its high hardness and ease of oxidation, present no advantages over gold stud bumps. However, Ag-alloy stud bumps exhibit satisfactory bondability and have been proposed as the optimal substitute for Au stud bumps to ensure better reliability in soldering and better intermetallic growth kinetics with Al bond pads. In this article, the intermetallic growth of Ag stud bumps alloyed with 2%, 10%, and 12% Pd after high-temperature storage tests (HTSTs) is investigated. The results indicated that the Pd atoms remained immobile in the bump-side matrix without diffusing into the aluminum pad side. Alloying with higher Pd content enhanced the formation of the favorable Ag2Al intermetallic compound (IMC), whereas lower Pd content resulted in severe cracking due to the formation of Ag3Al IMC. Compositional analysis showed that continuous layers of Ag–Al IMCs doped with large amounts of Pd formed at the interfaces close to the Ag stud bumps, but no Pd was detected on the Al pad side. The bonding strength increased after aging at 150 °C and 200 °C for 200 h, but it decayed drastically after aging at 250 °C for 200 h. The relationship between intermetallic growth and failure mode was established.

Purpose The purpose of the study is to investigate the spatial aspects of underfill flow during the flip-chip encapsulation process, for instance, meniscus evolution and contact line jump (CLJ). Furthermore, a spatial-based void formation mechanism during the underfill flow was formulated. Design/methodology/approach The meniscus evolution of underfill fluid subtended between the bump array and the CLJ phenomenon were visualized numerically using the micro-mesh unit cell approach. Additionally, the meniscus evolution and CLJ phenomenon were modelled analytically based on the formulation of capillary physics. Meanwhile, the mechanism of void formation was explained numerically and analytically. Findings Both the proposed analytical and current numerical findings achieved great consensus and were well-validated experimentally. The variation effects of bump pitch on the spatial aspects were analyzed and found that the meniscus arc radius and filling distance increase with the pitch, while the subtended angle of meniscus arc is invariant with the pitch size. For larger pitch, the jump occurs further away from the bump entrance and takes longer time to attain the equilibrium meniscus. This inferred that the concavity of meniscus arc was influenced by the bump pitch. On the voiding mechanism, air void was formed from the air entrapment because of the fluid-bump interaction. Smaller voids tend to merge into a bigger void through necking and, subsequently, propagate along the underfill flow. Practical implications The microscopic spatial analysis of underfill flow would explain fundamentally how the bump design will affect the macroscopic filling time. This not only provides alternative visualization tool to analyze flow pattern in the industry but also enables the development of accurate analytical filling time model. Moreover, the void formation mechanism gave substantial insights to understand the root causes of void defects and allow possible solutions to be formulated to tackle this issue. Additionally, the microfluidics sector could also benefit from these spatial analysis insights. Originality/value Spatial analysis on underfill flow is scarcely conducted, as the past research studies mainly emphasized on the temporal aspects. Additionally, this work presented a new mechanism on the void formation based on the fluid-bump interaction, in which the formation and propagation of micro-voids were numerically visualized for the first time. The findings from current work provided fundamental information on the flow interaction between underfill fluid and solder bump to the package designers for optimization work and process enhancement.

Copper is a commonly used interconnect metal in microelectronic interconnects due to its exceptional electrical and thermal properties. Particularly in applications of the 2.5 and 3D integration, Cu is utilized in through-silicon-vias (TSVs) and flip chip interconnects between microelectronic chips for providing miniaturization, lower power and higher performance than current 2D packaging approaches. SnAg capped Cu pillars are a common high-density interconnect technology for flip chip bonding. For these interconnects, specific properties of the Cu surface, such as roughness and cleanliness, are an important factor in the process to ensure quality solder bumps. During electroplating, tight processing parameters must be met so that defects are avoided, and high bump uniformity is achieved. An understanding of the interactions at the solder and Cu pillar interface is needed, based on the electroplating parameters, to determine the best method for populating solder on the wafer surface. In this study, surface treatment techniques such as oxygen plasma cleaning were performed on the Cu surfaces and the SnAg plating chemistry for depositing the solder were evaluated through hull cell testing to qualitatively determine the range of current densities to investigate. It was observed that current density while plating played a large role in solder bump deposition morphology. At the higher current densities greater than 60 mA/cm2, bump height non-uniformity and dendritic growth are observed and at lower current densities, less than or equal to 60 mA/cm2, uniform, continuous bump height occurred.

A huge shift in classical system integration composed of heterogeneous and homogeneous substances from 2D to 2.5D or even 3D assembly is a promising solution to satisfying the requirements of electronic packages, such as high operating speed, multifunctionality, and low form factor, under the physical limits of nanoscaled transistors and bottlenecks in related fabrication technologies. However, considerable dimension mismatch is introduced into the entire packaging by numerous microbumps ( ${\mu }$ -bumps) with complicated compositions in existing frameworks. In addition, failure location and precise reliability estimation are difficult to achieve when the layout of high-density ${\mu }$ -bump arrays is considered. To solve this urgent issue, an equivalent material characteristic methodology for ${\mu }$ -bump arrays based on finite element analysis (FEA) is developed in this study. A test vehicle for chip-on-chip packaging with wafer-level underfill is set up to obtain the mechanical characteristics of equivalent materials for the portion with internal ${\mu }$ -bump arrays. The equivalent plastic strain generation of the tin layer is simulated by systematically comparing the numerical convergence of FEA under the assumption that the lead-free solder forms ${\mu }$ -bumps within after the assembly process. Analytic results indicate that at least four rows of actual ${\mu }$ -bumps from the outermost edge of the ${\mu }$ -bump array are required to ensure numerical accuracy in contrast with the result obtained from the actual model of the present packaging structure.

Molded underfill process provides many benefits for higher productivity and lower cost over the conventional capillary underfill process. However, the void defects in a molded underfill process could cause pop-corning effect and solder extrusion during the reflow process. This paper presents a highly efficient and accurate hybrid model that can be applied to diagnose the void risk in vacuum molded underfill processes of real flip-chip, package-on-package devices with complex ball arrays and large PCB strips. The model combines multi-zone porous media model, Hele-Shaw model and compressible two-phase computational fluid dynamics model. The model has been well validated in terms of the entrapped void size and its behavior with flow visualization experiments. Also, a set of parametric studies on a FC-POP molded underfill flow process were performed to pre-assess the future node’s molded underfill process. Not only the model provides a better understanding of the physics of void entrapment but also it is proven to be an effective tool for assessing the potential void risk through its application to 10nm flip-chip, package-on-package device manufactured in mass production line.

This article investigates how floor plan layout of a printed circuit board (PCB) influences the reliability of the component's solder joint connections when operated in a vibrating environment. A random vibration profile as seen in an automotive environment was used in full lifetime tests. An industry-standard FR4 PCB with electroless nickel immersion gold (ENIG) surface finish was manufactured with double-sided component placement including 14 flip chips, eight on the top side and six on the bottom side. Ultrasound scans were used as a nondestructive test to assess the integrity of solder joints from manufacture to failure. This enabled monitoring of the important interface between solder joints and flip chip where failure mostly occurs. The initial failure pattern was found by experiment where 86 cycles of random vibration caused all flip chips to mechanically fail. Failure followed a Weibull probability with a value of β = 1.297, indicating that failure rates increase with time. The results show that the reliability of a flip chip varies with its position on a PCB with some marked differences to component lifetimes. The results also show that for two-sided flip-chip placements on a PCB, back-to-back, overlapped, and single-sided orientations have subtle effects on flip-chip lifetimes. Similarly, reliability varied with solder joint positions since joints on the sides of a flip chip nearest the PCB edges were less reliable than those on sides on a flip chip furthest away. Finally, design guidelines are offered to effect the most reliable flip-chip placement on a two-sided PCB when operated in a vibrating environment. © 2011-2012 IEEE.

In this article, flip chip assembly using nonconductive films (NCFs) was evaluated for chip-on-board (COB) packages using Cu/Sn–Ag hybrid bumps. In general, significant thermomechanical stress can be induced at the Cu-pillar/Sn–Ag solder joint because of a large coefficient of thermal expansion (CTE) mismatch between the Si chip and printed circuit board (PCB). If a concave-shaped solder joint morphology is generated at the solder joint, thermomechanical stress could be concentrated at the solder joint, resulting in an early failure of T/C reliability. To obtain the solder joint morphology without a concave-shaped solder joint, NCFs’ curing properties and viscosity should be controlled. In particular, the NCFs’ viscosity at the solder melting temperature, at which metallurgical bonding between molten solder and Cu pads occurs, will significantly affect the solder joint morphology. For this reason, solder joint formation was investigated at each viscosity of NCFs and bonding temperature during the thermo compression (TC) flip chip bonding process. In addition, specific viscosities at certain bonding temperatures during the flip chip bonding process were obtained from measured degrees of cure and viscosity approximation. Finally, the material properties of NCFs were optimized without NCF traps at the solder joint and concave-shaped solder joint, and T/C reliability was evaluated for each silica powder content. As a result, it was confirmed that the COB packages using Cu/Sn–Ag hybrid bumps and optimized NCFs show stable resistance changes within 10% of the initial resistance after the T/C reliability test.

This article provides a novel 3-D die-to-wafer (D2W) bonding method using intermetallic compound (IMC) layer insertion into a soft Sn bump to generate mechanical connection of two dies, called insertion bonding. A 50% decrease in stacking time can be obtained. Using this process close to a 100% electrical yield of daisy chains containing 800 fine pitch bumps (20 $\mu \text{m}$ ) is achieved. Various challenges for insertion bonding, such as material selection, surface properties of microbumps, bonding optimization, and compatibility with underfill materials, are discussed in this article. In addition, the potential application of IMC insertion bonding to prevent oxide formation for Co-based under bump metallization and as protection layer is explored.

Purpose The purpose of this study is to investigate the effect of the adhesive force and density ratio using lattice Boltzmann method (LBM) during underfill process. Design/methodology/approach To deal with complex flow in underfill process, a framework is proposed to improve the lattice Boltzmann equation. The fluid flows with different density ratio and bump arrangement in underfill are simulated by the incorporated Carnahan–Starling (CS) equation of state (EOS). The numerical study conducted by finite volume method (FVM) and experimental results are also presented in each case at the different filling percentage for verification and validation purpose. Findings The numerical result is compared well with those acquired experimentally. Small discrepancy is detected in their flow profile. It was found that the adhesive force between fluid and solid was affected by the density ratio of the fluids and solder bump configuration. LBM has shown better adhesive force effect phenomenon on underfill process compared to FVM. LBM also demonstrated as a better tool to study the fluid flow in the underfill process. Practical implications This study provides a basis and insights into the impact of adhesive force and density ratio to the underfill process that will be advancing the future design of flip chip package. This study also provides superior guidelines, and the knowledge of how adhesive force is affected by flip chip package structure. Originality/value This study proposes the method to predict the adhesive force and density ratio effect for underfill flow in flip chip package. In addition, the proposed method has a good performance in representing the adhesive force during the underfill simulation for its natural physical basic. This study develops understanding of flow problems to attain high reliability for electronic assemblies.

Purpose In line with the recent development of flip-chip reliability and underfill process, this paper aims to comprehensively investigate the effect of different hourglass shape solder joint on underfill encapsulation process by mean of experimental and numerical method. Design/methodology/approach Lattice Boltzmann method (LBM) numerical was used for the three-dimensional simulation of underfill process. The effects of ball grid arrays (BGA) encapsulation process in terms of filling time of the fluid were investigated. Experiments were then carried out to validate the simulation results. Findings Hourglass shape solder joint has shown the shortest filling time for underfill process compared to truncated sphere. The underfill flow obtained from both simulation and experimental results are found to be in good agreement for the BGA model studied. The findings have also shown that the filling time of Hourglass 2 with parabolic shape gives faster filling time compared to the Hourglass 1 with hemisphere angle due to bigger cross-sectional area of void between the solder joints. Practical implications This paper provides reliable insights to the effect of hourglass shape BGA on the encapsulation process that will benefit future development of BGA packages. Originality/value LBM numerical method was implemented in this research to study the flow behaviour of an encapsulation process in term of filling time of hourglass shape BGA. To date, no research has been found to simulate the hourglass shape BGA using LBM.

Internet of Things (IoT) accelerated by the rapid progress of 5G is bringing a lot of challenges to semiconductor packaging technologies. In particular, flip-chip bonding technology is strongly required to realize ultrafine-pitch products, such as network, graphic, and artificial intelligence (AI) processors. Thermal compression bonding (TCB) with pre-applied underfill materials, such as nonconductive paste or nonconductive film (NCF), has been expected as one of the effective solutions for these applications for a long time. Nevertheless, the actual availability is still limited due to its high process cost. In other words, innovative breakthrough to achieve reasonable TCB cost is necessary to support the expansion of IoT. So far, some kinds of multiple die bonding processes represented by collective bonding have been proposed and demonstrated with conventional NCFs. However, it is becoming clear that the conventional NCFs optimized as fast cure type are very difficult to have enough processability for the multiple bonding processes due to mismatch between reactivities of the materials and bonding process conditions. That is why the new NCF dedicated to the multiple die bonding processes has been developed in this article. The developed NCF was designed to survive long-time thermal exposure on a bonding stage so that the collective bonding could be completed with reasonable process margin. To achieve target specifications, this article has started with the design of a new resin composition applied to the developed NCF. Then, basic properties required for NCFs, such as thermal stability and electrical insulation, were investigated in feasibility studies. Finally, TCB was demonstrated, and reliable solder joints were formed without any abnormality even after extended thermal exposure on the bonding stage. Moreover, it was found that the developed NCF might have the potential to achieve void-free encapsulation by pressure curing.

With the advent of the 5G era, power devices and telecom equipment require small form factor and excellent thermal performance. Flip-chip Land Grid Array (FC-LGA) is rapidly becoming the package choice for those devices, because of its low RDS (ON) and high frequency operation. However, it also brings great challenges to reliability design. Large number of flip chip solder joints between die and substrate lead to a more rigid package body, which will accumulate strong thermomechanical stress under alternating temperature and so inevitably trigger package reliability issues. Excessive warpage and body crack will occur if without appropriate package design consideration. In this study, the thermo-mechanical behaviors of FC-LGA were investigated by finite element simulation under different TCC conditions. Due to the complexity of the LGA substrate, the simulation with detail substrate model in use will incur expensive computation. This work proposed a simplification method considering a substrate of complicated structure as an equivalent anisotropic volume. With simulation models simplified, DoE study was performed to investigate the influence of packaging materials and geometry on the thermo-mechanical reliability of FC-LGA packages in high efficiency. A higher die-to-EMC thickness ratio will result in a more severe package convex warpage, while using a thinner die and a thicker EMC layer can prevent package body from cracking during heating or cooling processes. Besides packaging geometry, the influence of substrate layouts and EMC mechanical properties were also studied to find the optimal packaging design to mitigate the risks of excessive package warpage and body crack.

Today's flip chip scale packaging (FCCSP) microelectronics products are becoming more and more complex, especially in the packaging process using molded underfill manufacturing, which reduces the cost of flip chip technology such as molded underfill (MUF) High, provides molding ability in molding. The problem is to leave effective space under the chip. Generally speaking, this requires a lot of experimental DOE (chip size, substrate design, and epoxy resin type) to solve this problem. For the reasons mentioned above, mold-flow simulation software can be applied to use different flow condition to obtain the best solution as the MUF FCCSP of the substrate structure design. Such a simulation method can help shorten the product development cycle. This article uses the commonly used 3D molding process simulation software for transferring manufacturing process parameters. This article will introduce a comparison of two different structures. A MUF is FCCSP, it is matched with different bump height (SOH) structure comparison (control the flow of different chip bottom space), and observe the difference of the flow melt-front. The second is that there are two different designs on the surface of the substrate (welding masks with completely open or partially open patterns) through the table to enter the previously separated welding mask samples (welding masks with l0um depth structure) to maintain different modes. As this research, we can get a lot of conclusion that improve the molding capability of molded underfill FCCSP in the transfer molding process. If the bottom of the molded underfill FCCSP chip is matched with a structure with a height of 55 µm, then the molding epoxy can easily flow under the area with a large flow space, so the risk of entrapment can be reduced. In addition, the molding compound also has good melt front fluidity, and the fully open substrate surface design of the substrate solder resist layer can achieve more l0µmm space underneath the die area. Then, the CAE output are consistent as the experiment and it can to predict whether the product has a risk assessment of void.

The solder resist crack root cause and methods to prevent it were studied. Solder resist crack with solder extrusion was observed in the sample package after solder ball mount. A finite element model was developed to simulate the solder resist stress. A high stress area at the bump pad edge was observed at the reflow peak temperature, which is the solder resist crack root cause. The factors affecting the solder resist stress were also studied via the finite element method. It was found that reflow temperature, underfill Young's modulus, substrate dielectrics CTE, and die-to-substrate ratio are the key factors to the solder resist stress. Strategies of using low Young's modulus underfill and small die-to-substrate ratio to reduce solder resist crack length were demonstrated through process DOE and design optimization in the test vehicle package.

The electromigration (EM) of Cu/Sn-Ag1.8/Ni/Cu flip chip Cu pillar bumps structure under DC stress and bidirectional pulse current stress is studied. The temperature, thermal gradient and stress distribution of Cu pillar bumps under different current stress are obtained by ANSYS finite element simulation. Two groups of EM experiments under different current stress were carried out. At 125°C and ${3.5\times} {10^{4}\mathrm{A}/\text{cm}^{2}}$ , the resistance change rate of Cu pillar bumps under bidirectional pulse current stress was about 1/5 of the DC stress. After 220h of EM experiment, the bumps were completely alloyed into ${\text{Cu}_{6}\text{Sn}_{5}}$ and ${\text{Cu}_{3}\ \text{Sn}}$ under DC stress, and the polarity phenomenon appeared on the Ni layer and Cu pad at the cathode side. However, under the stress of bidirectional pulse current, the growth rate of intermetallic compound (IMC) is obviously slow, there is a small amount of solder remaining in the bump and the solder is biased to the side of the Ni layer, and the Ni layer does not show obvious polarity phenomenon. At the same time, combined with the simulation, it is found that the Cu trace may also become a weak link of the reliability of the Cu pillar bump.

This paper presents the design, simulation and fabrication process of a phase array ultrasonic transducer based on 1mm-thick lead zirconate titanate (PZT) substrate with 128 independently accessible electrodes through flip chip bonding with indium solder bump. The reflow processes of indium have been explored under air, nitrogen, hydrogen, liquid metal flux, and formic acid (H 2 CO 2 ). Among these, formic acid is found to be the best ambient for forming indium bump, as it removes indium oxide and clean out residuals most effectively. Also, different sizes of under bump metallization (UBM) and indium pattern have been tested, and the measured heights of indium bumps after a reflow show that the lateral dimension ratio of 1:2.5 between the UBM and indium patterns offers the best wettability over the UBM with the smallest residual.

Moore's law has been slowed down in transistor scaling, but the demands of high computing processing does not cool down and the data rate transmission is growing exponentially in each day. The surge in high data rate causes present DDR4 memories succumb to this horrendous needs. High bandwidth memories (HBM) are then developed to fulfill these requirements. The upended trends drive up chiplets integrated package evolution. Presently most of these chiplets integrated packages are either homogeneously or heterogeneously packed together using 2.5D or Fan-Out-Multi-Chip Module. And these packages contain of micro bump pitches at the range of $40\sim 55 \mu \mathrm{m}$ . While HBM package are either stacked by 4 or 8 heights of memories dies with bump pitch of $40 \mu \mathrm{m}$ . Hybrid bond are then developed for much higher I/O density. However, hybrid bond technology has better economic values for bump pitch which is equal or below than $10 \mu \mathrm{m}$ . There is a grey area of bump pitch between $10\ \mu \mathrm{m}$ to $55\ \mu \mathrm{m}$ . Shall this package be assembled by hybrid bonding, reflow soldering, or thermal compression bonding (TCB)? The main challenges of this fine micro bump interconnections come with bump coplanarity, Kirkendall void formation and capillary underfill flow between the chip to chip spaces. This paper provides the answers to these challenges. A 3D package with $20 \mu \mathrm{m}$ bump pitch using chip to wafer stacking is developed. There are two test vehicles: TV 1 and TV 2 under the same conditions of $6.5^{\ast} 10.1\ \text{mm}^{2}$ in top chip, $10.1^{\ast} 11.1\ \text{mm}^{2}$ in bottom chip, $13\ \mu \mathrm{m} (\text{diameter})/20\ \mu \mathrm{m}$ (pitch) bump. TV 1 uses solder reflow as stacking technology while TV 2 uses TCNCF (Thermal Compression Non Conductive Film.) Two types of bonding technologies are applied for comparison, which are solder reflow and thermal compression bonding (TCB). The test vehicle consists of 2 stacked chips, with die thickness of $70 \mu\mathrm{m}$ each. Top chip is first singulated and then placed on second chip at a wafer formed. Prior to the placement, the bump coplanarity is collected prior to placement. The chip-to-wafer bonding are then established by reflow soldering and TCB. Underfill is dispensed to the chip to chip gap is characterized. Optimized underfill materials are then applied to subsequent process. Followed by molding and grinding top chip to $70\ \mu \mathrm{m}$ thick. The stacked up chip modules are then placed on substrate using conventional flip chip process. The final packages are first electrically tested then stressed up to 10 times reflows and high temperature storage at 150 °C for 1000 hours. At the interim of readouts, the units were electrically verified prior to cross section. With the optimized conditions, 3D package has been successfully passed above thermal stress without Kirkendall void formation. In this paper, results of the bump coplanarity, characterization of underfill flow, and Kirkendall void inside the micro bump are presented and discussed. Cross-section of the micro bump before and after reliability tests will be shared.

Thermal interface materials (TIMs) have been widely adopted for improved thermal dissipation in flip chip ball grid array (FCBGA), flip chip lidded ball grid array (FCLGA) and flip chip pin grid array (FCPGA) packaging. As the next generation devices' requirements for power get even higher, enhanced thermal performance at the package level is increasingly important. A typical TIM applies a polymer type, but the current polymer TIM products are insufficient to meet the advanced product roadmap requirements due to lack of thermal conductivity, TIM delamination on large size die, unstable process workability and other reasons. Even potential candidates for a high thermal conductivity TIMs, such as silver (Ag)-Sintered TIM and graphite sheet have difficulties covering all the development goals of a large body package due to high thermal resistance, poor TIM coverage or too thick bond line thickness (BLT). To meet the high-end central processing unit (CPU) market's needs, an indium (In) TIM has been selected for FCLGA or FCPGA products. A pure indium TIM has a low liquidus point and provides a good way to reduce stress during In TIM soldering. However, this characterization of Indium TIM could be a weak point for FCBGAs which need an additional reflow process after TIM and lid attachment. TIM re-melting could occur during the reflow process and affect TIM coverage, cause delamination and create a component shortage issue. This is one of the main reasons that a pure indium TIM is hard to apply on FCBGA devices. In this paper, a metal TIM (In and tin (Sn) alloy) will be discussed as a solution for next generation FCBGAs that have a large body size and require high thermal conductivity. These new alloy TIMs are expected to provide better thermal dissipation performance due to both a “high liquid phase point” and a “low solid phase point.”.

Advanced package technology has been developed rapidly to meet a demand of the high end application such as AI and datacenter. 2.5D silicon interposer technology has been focused as the solution, for high end applications because of its heterogeneous device integration compatibility: high bandwidth memories (HBMs), logic devices or functional chiplets. In this study, a 2.5D structure package called Molded Interposer on Substrate (MIoS) with an extremely large silicon interposer (>2800mm2) on the $85\times 85\text{mm}^{2}$ body size assembled with 2-ASICs and 8-HBMs was demonstrated successfully for higher chip integration capability. Also, the key challenges of extremely large size 2.5D MIoS package such as warpage of the molded interposer (MIP) module and high level of reliability subjected to thermo-mechanical stress were investigated. MIP warpage was simulated by finite element method (FEM) and controlled the warpage difference between MIP and substrate below 50um at solder melting temperature. As a result, the number of 60K bumps obtained the good joint quality during reflow bonding process. The package reliability was evaluated under thermal cycle test (−55∼125°C) for optimizing the stress induced by the mismatch of thermal expansion (CTE) of components: substrate, underfill, ring frame materials and epoxy mold compound (EMC). The primary failure modes were underfill crack and EMC crack at the corner of devices at the early stage but, through a study on components material properties, package level reliability was improved.

Capillary Underfill (CUF) process has been widely used in flip-chip packaging since it offers significant improvement of the solder joint reliability. This study focuses on the underfill flow behavior of a multi-chip module with a cavity in the laminate substrate designed for heterogeneous integration. In this paper, Computational Fluid Dynamics (CFD) simulation with a three-dimensional model is developed to analyze the flow motion of the underfill, while considering several parameters that affect the capillary action. Simulation results are validated with a flow visualization experiment by using transparent glass chips and substrates. The results of time-developing behavior of underfill filling are compared between the simulation and experiment and good agreement is shown. In addition, several factors affecting the capillary action such as surface tension, contact angle, viscosity were evaluated in the CFD analysis. It was revealed that those factors have large influence on the flow and the void formation inside of the cavity. The present analysis is useful for selecting the underfill with optimal material properties for successful filling process.

Thermo-mechanical reliability of Flip Chip Ball Grid Arrays in automotive underhood environments has received a lot of attention owing the emergence of new application in advanced driver assist systems including guidance, navigation and control. The reliability and the extended time survivability of the materials and interfaces in the advanced package architectures is not well understood. In this paper, the effect of four different developmental underfill encapsulant properties on flip chip bumps and solder balls were investigated using lidded FCBGA model. The material properties of the developmental underfills which have been measured in a prior study by the authors, have been used for the purpose of modeling. The effect of the underfill properties on the plastic work in the package-level solder joints and chip-level solder joints has been modeled under the automotive thermal cycle of −40 to +125°C. . Each cycle is of 2 hours and consist of 40 and 20 minutes of ramp and dwell times, respectively. Interaction of the material properties on the plastic work on the flip-chip solder joints and the package-level joints has been examined. The results have been computed for packages with and without a compressive heat sink. Non-linear interconnect material models have been used for both chip-level and package-level interconnects. Anand viscoplasticity has been used for modeling the interconnects and the hysteresis loops studied as a function of the underfill properties.

The demand for high-performance semiconductor products in line with the development of information technology industry continues to increase. However, fab node shrinkage, which led the development of semiconductor performance in the past, has reached its limit. As a result, the need for multi heterogeneous chip integration technology is rapidly increasing. 2.5D packaging using Si interposer is one of these. The biggest difficulty in the development of 2.5D packaging is to overcome the warpage of multi-chip (including HBM, chiplet, etc.) integrated interposer. The first challenge is improving warpage caused by increase in the size of the interposer. Increasing the number of integrated chips is essential for improving the performance of the 2.5D package. On the other hand, this causes an increase in the size of the interposer, and the warpage increases as well. The second problem is unique warpage shape of the interposer. Unlike the conventional monolithic chip, the 2.5D interposer exhibits a variety of unique warpage shapes depending on the design. So it's not enough to simply reduce the size of the warpage. These problems are limited in overcoming them through material composition and design, so a way to overcome them through process technology is needed. In this study, the warpage behavior of multi-chip integrated interposer was analyzed, and a novel bonding technique which handle highly warped interposer was studied. To prevent non-wetting during bonding process of very highly warped interposer we devised a novel technique which can bond the chips overcoming limit of warpage. The actual measured warpage was 182um that bonding was impossible with conventional mass reflow. To overcome this, continuous loads were applied on the top of the interposer and high activity flux was used to induce stronger solder collapse in the direction of the substrates. As a result, bonding with mass reflow was possible even in interposer with severe warpage.

Semiconductor package sizes are getting smaller and bump pitches narrower while the number of input/output (I/O) continues to increase. The traditional flip-chip process, which assembles the chip with copper (Cu) pillar interconnects to the substrate using a mass reflow technique faces several hurdles as package dimensions become more challenging. These include high stress between low-k die and substrate, die shift, and die cracking when the pitch is narrower than $\mathrm{100}\ \mu\mathrm{m}$ . The thermocompression bonding (TCB) process can help overcome these challenges. Pre-applied underfills like non-conductive paste (NCP) and non-conductive film (NCF) enable the TCB process. NCP is applied directly on the substrate, while NCF is applied on the wafer prior to TCB. This paper discusses the key material properties and TCB parameters that are critical for good solder joint formation and void-free gap-filling. During the NCP TCB process, void issues are common and several factors (e.g. dispensing volume and pattern, bonding parameters and material properties) contribute to void formation. In this study, different dispensing patterns were evaluated to better understand this issue. Based on the experimental results, specific patterns appear to help reduce voiding. In terms of TCB process, focus was on the effect of bond speed on void performance. The speed of pushing out the NCP clearly affected the flow of NCP & void performance. Similarly, TCB process for NCF also require setting the right bond parameters to ensure good solder joints and zero void performance. Three key parameters were studied for bond optimization: bond force, contact temperature, and ramp rate. A wide range of bond forces, contact temperatures, and ramp rates were chosen for the experiments. After performing the TCB process, joint shape and void performance via CSAM were evaluated. Based on the study, an optimal condition was identified for better application performance. Subsequently, reliability tests such as MSL (85° C/85% RH) and uHAST were conducted.

In order to support the high growth of Artificial Intelligence, Internet of Things, Industrial IOT, Cloud Service and 5G, the IC (Server/Router/Switch) needs higher/faster performance to collect, store, commute and transmit a mass of data. Therefore, the I/O (input/output) density of IC will increase with the silicon nodes $\mu\text{bump}$ , and fine line width/space substrate. However, the solder reflow of IC faces two problems of the chip damages (silicon nodes: current leakage, highly electromigration; ELK (extremely low-k): current leakage, crack) and solder high stress (solder: wicking, IMC (intermetallic compound)) due to highly thermal budget of MR (mass reflow). In this paper, LAB (laser assisted bonding) will replace MR (mass reflow) to solve these problems. In this study, a test vehicle with the size of $55^{\ast}55\ \text{mm}2$ FCBGA (flip chip ball grid array) was built. Two types (A and B) of substrate were applied to the FCBGA, with the differences between the solder mask (thickness, surface brightness/roughness) and substrate mass. LAB uses a semiconductor laser with wavelength of 980 nm, and the area of laser beam is 91.5% of the substrate area. The study is divided into three parts. For the first part, the surface temperature of die without substrate is higher than that of die with substrate at the same parameters about 187.2 °C. The result shows that the substrate has the function of heat storage. In addition, for the surface temperature of die with substrate, the result shows that all solders melt at 2.82 sec, and the surface temperature of the center of die is 22.8 °C lower than the four corners of it. Then the delta temperature between the surface temperature of the center of die and bump is 48.3 °C. The result shows that the overall temperature of die with substrate is not uniform. Next, for substrate effect, the surface temperature of die and B substrate is lower than that of die and A substrate based on the following reasons: for the solder mask, (a) the surface brightness of B substrate is 11% higher than that of A substrate result in an increase of the reflected light; (b) the roughness of B substrate is 26% lower than that of A substrate result in an increase of the reflected light; (c) the thickness of B substrate is 23% lower than that of A Substrate result in a reduction of Absorbed light; for substrate mass (d) the weight of B substrate is 10% higher than that of A substrate. Finally, the assembled FCBGA packages by LAB passed reliability tests: MSL4 pre-conditioning with uHAST 168 hours, TCT B 1000 thermal cycles and HTST 1000 hours. Details of the results are presented and discussed in the paper. In summary, we have developed the parameter set to solve it in different substrates and predicted the melting time of solder and temperature profile of die surface. Therefore, LAB (laser assisted bonding) can successfully solve the problems MR encounters. The full descriptions of the development results will be discussed in this study.

Because Cu-Cu bonding is the key technique in 3D IC packaging, its reliabilities will become issues in the future. In this study, Cu-Cu joints with underfill was fabricated by using instant bonding process, in which bonding conditions were under 31∼90 MPa at 300 °C for 10∼30 s. Several samples underwent two reliability tests: temperature cycling test (TCT) and electromigration (EM) test. These samples passed 1000 cycles TCT, and the measured EM life time was least 3 times longer than that of solder joints with similar dimension. Failure mechanisms of reliability tests were examined by cross-section images and finite element analysis. In TCT, cracks were formed at bonding interface because it is relative weak compared to the neighboring structures. For EM tests, voids were formed at passivation opening of joints with current crowding. The current study provides a fundamental understanding in the reliabilities of Cu/organic dielectric hybrid bonding structures.

Cu pillar bump offers a number of advantages for flip chip packaging, compared to the conventional solder bump. However, due to its rigidity structure, Cu pillar bump introduces a lot of stress to the chip, which causes the failure of packaging structures, especially for the advanced node devices which typically have brittle low K dielectric material. In this paper, for the first time we propose two types of Cu pillar structures to reduce the stress. The first Cu pillar structure has bigger Cu dimensions at the base. The other one is designed to add an additional Cu pad under the Cu pillar bump. Finite element analysis is used to study the stress of the both structures, and it is found that with the increase in pillar bump contact area over the chip surface, the stress decreases in both structures. Results also indicate that the Cu pillar bump undercut induces higher stress, and thin Cu6Sn5 intermetallic compound has less impact on the stress during flip chip mount reflow. The study provides a novel way to improve the reliability by reducing the stress in the Cu pillar bump related packaging.

Purpose This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization. Design/methodology/approach The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number. Findings Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency. Practical implications The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments. Originality/value The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.

IBM has developed and has been enhancing the injection molded solder (IMS) technology as an advanced solder bumping technology with flexible solder alloy composition applicable even to fine pitch and small diameter systems. IMS is a simple bumping technology that can form solder bumps by injection of molten solder into via holes patterned in a photoresist layer. IMS is applicable to formation of solder caps for Cu pillar bumping which is a technology widely used for fine pitch applications. One of the advantages of IMS is the capability of using ternary, quaternary, or more compositions solder alloys for bumping, which is not achievable by current plating technology. In this study, the feasibility of IMS bumping and flip chip joining with quaternary solder alloys is demonstrated through assembling of 2.5D package test vehicles using low melting temperature (135°C) SnBi based quaternary alloy solder and associated reliability test. The test vehicles passed the 2250 cycles criteria of thermal cycling test and the observation of microstructures showed that there is no significant crack at the solder joints after flip chip joining or after the 2250 cycles of thermal cycling test. In addition, the tensile test on SnBi based quaternary alloy solder, Sn-58wt%Bi-2.0wt%In with small amount of Pd (less than 1wt%) was conducted using fine diameter specimens. From the SS curve obtained from the test, Young's modulus of the solder was determined as 7.3 GPa and 0.2% proof stress was obtained as 73 MPa both at 25°C. The creep property of the solder was evaluated and the constants for Norton's creep law for the solder were determined at 25, 80 and 110°C. The microstructure observation and Energy Dispersive X-ray (EDX) analysis of the flip chip joints revealed the formation of a thick bismuth (Bi) layer between CuSn intermetallic compound (IMC) layers within a joint. The mechanical simulation of the 2.5D test vehicles showed that the thermomechanical stress of a flip chip joint with Bi/CuSn IMCs at thermal cycling condition is comparable to those of CuSn IMC or Sn-3.0Ag-0.5Cu (SAC305) solder joints consistent with the thermal cycling test result. The advantage of using low temperature quaternary solder materials in flip chip packages is confirmed by mechanical simulation of 2D packages at reflow condition which showed lower stress on low-k dielectric layers for the packages with quaternary solder joints than for the packages with SAC305 solder joints.

Plating Solder bump is one of the key enabling technologies for flip chip assembly methodology. Flip chip assembly has advanced to support higher levels of interconnect and small feature sizes. Electroplating is a very promising technology for finer bump features when compared with solder printing and ball mounting. Hence, the plated-solder bump morphology is quite important for process quality control and design realization. This paper aims to study the plated solder behavior from as-plated mushroom structure to after reflowed bump stage photoresist sizing. In addition, this activity will consider the full bumping process integration relative to the electroplated solder bump design rules.

In a fine pitch flip chip package, a laser-assisted bonding (LAB) technology has recently been developed to overcome several reliability and throughput issues in the conventional mass reflow (MR) and thermal compression bonding technology. This study investigated the LAB process for a flip chip package with a copper (Cu) pillar bump using numerical heat transfer and thermo-mechanical analysis. During the LAB process, the temperature of the silicon die was uniform across the entire surface and increased to 280 °C within a few seconds; this was high enough to melt the solder. The heat in the die was quickly conducted to the substrate through the Cu pillar bumps. Meanwhile, the substrate temperature was low and remained constant. Therefore, a stable solder interconnection was quickly achieved with minimal stress and thermal damage to the package. The substrate thickness, the number of Cu bumps, and the bonding stage temperature were found to be important factors affecting the heat transfer behavior of the package. The temperature of the die decreased when a thinner substrate, a higher number of Cu bumps, and a lower bonding stage temperature were used. If the temperature of the die was not sufficiently high, insufficient heat was transferred to the solder to melt it, resulting in incomplete solder joint formation. Thermo-mechanical analysis also showed that the LAB process produced lower warpage and thermo-mechanical strain than the conventional MR process. These results indicated that a LAB process using a selective local heating method would be beneficial in reducing thermo-mechanical stress and increasing throughput for the fine pitch flip chip packages.

Creep tests were performed using a fixture composed of a spring, a micrometer and a heating pad to apply both heat and constant compressive load and elevated temperature to the actual solder joint. A microscopic digital image correlation technique was used to measure creep strains. A full-field deformation map of the cross-sectioned solder joint was generated as different constant loads were applied under different isothermal conditions on Sn3.0Ag0.5Cu flip chip ball grid array solder joints. Nonlinear regression was used to generate constitutive properties using the Garofalo hyperbolic sine model. The obtained constitutive properties were used to perform a finite element analysis simulation to compare the model with experimental results, which showed good agreement.

In addition to traditional high temperature eutectic soldering, the use of underfill epoxy to glue the electronic components to the PCB (memory, CPU, cryptographic chips) has now become the norm among mobile phone manufacturers, e.g. Apple, BlackBerry and Samsung. Currently, this technique is the best solution to protect components against various mechanical stresses and improve reliability. Unfortunately, traditional techniques (chip-off or lapping) have become impossible to apply to underfilled components without destroying them or without moving peripheral electronic components. These component movements make the board unusable or require many hours of expensive repairs and specific hardware. Acids and their use can be of interest in the digital forensics domain. Firstly, they can be used to de-capsulate the packaging of the electronic components before reading the chip (physical dump by chip-on), or to carry out reverse engineering of secure systems by micro-reading techniques of the silicon chip. Moreover, as we show in this paper, with the arrival of the latest generations of mobile phones, acid mixtures can be of interest if investigators want to use classical chip-off method (or the legal transplantation of damaged phones) for phones using underfill epoxy which cover the neighbouring components together (CPU, memory, capacitors, etc.). This work introduces a new method called “underfill acid corrosion”. The proposed process is based on the use of different mixtures of acids heated to various temperatures. We quantitatively study the influencing factors on the efficiency of acid corrosions on industrial underfill and present our results. Finally, we present our optimised process to unsolder electronic components which are glued together by an industrial high temperature underfill epoxy, without destroying the targeted electronic components and mobile phones PCB.

The intermetallic compound layers in solder bumps have the brittle feature and can easily fracture under thermal or mechanical loading. Therefore, the intermetallic compound is an issue for the fracture reliability of the solder bumps. In this work, the intermetallic compound growth before and after high temperature storage tests was investigated. The experiment results revealed that the solder bumps with nickel layers could reduce the intermetallic compound growth rate. The nickel layer, which was added in between Cu and SnAg for top solder bumps, was an important factor controlling the intermetallic compound thickness. It was hard to tell the intermetallic compound thickness at time zero; at the time of 147 hours, the intermetallic compound grew to 3.25 µm; at the time of 294 hours, the intermetallic compound grew to 5.25 µm. However, the solder joints were still in good condition.

Solder bumps realize the mechanical and electrical interconnection between chips and substrates in surface mount components, such as flip chip, wafer level packaging and three-dimensional integration. With the trend to smaller and lighter electronics, solder bumps decrease in dimension and pitch in order to achieve higher I/O density. Automated and nondestructive defect inspection of solder bumps becomes more difficult. Machine learning is a way to recognize the solder bump defects online and overcome the effect caused by the human eye-fatigue. In this paper, we proposed an automated and nondestructive X-ray recognition method for defect inspection of solder bumps. The X-ray system captured the images of the samples and the solder bump images were segmented from the sample images. Seven features including four geometric features, one texture feature and two frequency-domain features were extracted. The ensemble-ELM was established to recognize the defects intelligently. The results demonstrated the high recognition rate compared to the single-ELM. Therefore, this method has high potentiality for automated X-ray recognition of solder bump defects online and reliable.

Light-emitting diode (LED) devices depend strongly on proper thermal management to mitigate negative effects caused by high operating temperature, especially in general lighting applications. Flip-chip packaging has been used as a solution to reduce thermal resistance, with some iterations involving an epoxy underfill material to mechanically support solder joints and assist in thermal management. The benefits of underfill encapsulation on the thermal resistance of flip-chip LED (FCLED) packages have been studied, but the effects on optical performance have not been addressed. This paper identifies that the radiant power of the FCLED die suffers as a result of the underfill fillet. The selected underfill materials were applied to FCLEDs, and radiant power was measured. Radiant power was found to decrease as filler loading increased.