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Bonding distance is defined by the projected distance on a substrate plane between two solder points of a bonding wire, which can directly affect the morphology of the bonding wire and the performance between internal components of the chip. For the inspection of the bonding distance, it is necessary to accurately recognize gold wires and solder points within the complex imagery of the chip. However, bonding wires at arbitrary angles and small-sized solder points are densely distributed across the complex background of bonding images. These characteristics pose challenges for conventional image detection and deep learning methods to effectively recognize and measure the bonding distances. In this paper, we present a novel method to measure bonding distance using a hierarchical measurement structure. First, we employ an image acquisition device to capture surface images of integrated circuits and use multi-layer convolution to coarsely locate the bonding region and remove redundant background. Second, we apply a multi-branch wire bonding inspection network for detecting bonding spots and segmenting gold wire. This network includes a fine location branch that utilizes low-level features to enhance detection accuracy for small bonding spots and a gold wire segmentation branch that incorporates an edge branch to effectively extract edge information. Finally, we use the bonding distance measurement module to develop four types of gold wire distribution models for bonding spot matching. Together, these modules create a fully automated method for measuring bonding distances in integrated circuits. The effectiveness of the proposed modules and overall framework has been validated through comprehensive experiments. [ABSTRACT FROM AUTHOR]

This paper aims to develop a thermal fluid–structure interaction (FSI) methodology to study the effect of different Cu pillar bump diameters on thermal and mechanical performance during the reflow soldering process. The desktop reflow oven is modeled in ANSYS FLUENT, while the ball grid array (BGA) package assembly is modeled in ANSYS STATIC STRUCTURAL. The accuracy of the simulated reflow temperature profile has been verified by comparing it with the experimental temperature data, according to JEDEC standards. The temperature distributions of solder and Cu pillar bumps are compared. A parametric study has been conducted to analyze the effect of different Cu pillar diameters on the reflow soldering process. By coupling the thermal loads with the structural analysis using thermal FSI, Cu pillar bumps with a diameter of 0.20 mm are found to exhibit the lowest reflow temperature, minimum temperature difference, and minimum deformation and thermal stress, making them the most suitable interconnection joints for flip chip technology. The study also examines the effect of soldering materials on the Cu pillar bump. The findings of this research provide valuable insights into the effects of varying Cu pillar diameters on the reflow soldering process, which can help in the development of more reliable electronic assemblies. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) packaging using through-Si-via (TSV) is a key technique for achieving high-density integration, high-speed connectivity, and for downsizing of electronic devices. This paper describes recent developments in TSV fabrication and bonding methods in advanced 3D electronic packaging. In particular, the authors have overviewed the recent progress in the fabrication of TSV, various etching and functional layers, and conductive filling of TSVs, as well as bonding materials such as low-temperature nano-modified solders, transient liquid phase (TLP) bonding, Cu pillars, composite hybrids, and bump-free bonding, as well as the role of emerging high entropy alloy (HEA) solders in 3D microelectronic packaging. This paper serves as a guideline enumerating the current developments in 3D packaging that allow Si semiconductors to deliver improved performance and power efficiency. [ABSTRACT FROM AUTHOR]

Copyright of Journal of South China University of Technology (Natural Science Edition) is the property of South China University of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Gallium nitride (GaN) power devices have many benefits, including high power density, small footprint, high operating voltage, and excellent power gain capability. However, in contrast to silicon carbide (SiC), its performance and reliability can be negatively impacted by its low thermal conductivity, which can cause overheating. Hence, it is necessary to provide a reliable and workable thermal management model. In this paper, a model of a flip-chip packing (FCP) GaN chip was established, and it was assigned to the Ag sinter paste structure. The different solder bumps and under bump metallurgy (UBM) were considered. The results indicated that the FCP GaN chip with underfill was a promising method because it not only reduced the size of the package model but also reduced thermal stress. When the chip was in operation, the thermal stress was about 79 MPa, only 38.77% of the Ag sinter paste structure, lower than any of the GaN chip packaging methods currently in use. Moreover, the thermal condition of the module often has little to do with the material of the UBM. Additionally, nano-silver was found to be the most suitable bump material for FCP GaN chip. Temperature shock experiments were also conducted with different UBM materials when nano-silver was used as bump. It was found that Al as UBM is a more reliable option. [ABSTRACT FROM AUTHOR]

This paper presents the characteristics of signal transmission between a printed circuit board and an integrated circuit, which were obtained using a flip-chip bump process. To minimize signal loss occurring in an interconnection, a Sn-Au alloy soft bump having a diameter of 65 μm was used as the solder bump in the flip-chip process. The measurement result showed a return loss of less than 15 dB from DC to 43.5 GHz, and an insertion loss of 3.82 dB at 28 GHz. The measurements confirmed that it was very small within the measurement error range generated in the measurement environment of the insertion loss generated by the interconnection. This confirms good signal transfer performance across the DC to 43.5 GHz frequency band. Additionally, the study confirmed through meas- urement that all mm-Wave circuits developed in the Ka-band frequency range can be measured easily and accurately using a bound connector without a probe station requiring sophisticated control. [ABSTRACT FROM AUTHOR]

New diamond chip resistors have been used in high-power devices widely due to excellent heat dissipation and high-frequency performance. However, systematic research about their solder joint reliability is rare. In this paper, a related study was conducted by combining methods between numerical analysis and laboratory reliability tests. In detail, the shape simulation and thermal cycling finite element simulation for solder joints with different volumes were carried out. The optimized solder volume was 0.05 mm3, and the maximum thermal cycling stress under the optimized shape was 38.9 MPa. In addition, the thermal cycling tests with current and high temperature storage tests were carried out for the optimized solder joint, which showed good agreement with the simulation results, clarified the growth and evolution law of intermetallic compound at the interconnection interface, and proved the optimized solder joint had great anti-electromigration, temperature cycling and high temperature storage reliability. In this work, an optimized solder joint structure of a diamond chip resistor with high reliability was finally obtained, as well as providing considerable reliability data for the new type of diamond chip resistors, which would boost the development of power devices. [ABSTRACT FROM AUTHOR]

In this study, we report the effect of temperature on the microstructural evolution of flip chip solder joints under a temperature gradient of 2580 °C/cm at ambient temperatures of 100 °C, 125 °C, 150 °C, 160 °C, and 175 °C. The experimental results show that no microstructural evolution of un-stressed solders was found for samples tested at ambient temperatures of 100 °C and 125 °C, whereas thermomigration induced phase separation was observed for the samples tested at 150 °C, 160 °C, and 170 °C, suggesting that the thermomigration only occurred when the ambient temperature was higher than 150 °C. The theoretical derivation indicates that the threshold temperature difference needed to trigger thermomigration is found to be decreased with an increase in the ambient temperature. In addition, at a temperature gradient of 2580 °C/cm, the theoretical calculation indicated that a threshold temperature to trigger thermomigration is about 150 °C [ABSTRACT FROM AUTHOR]

In this subject, thermosonic flip-chip technology was introduced to conduct low-temperature bonding of Ag paste and chip interconnection experiments with micro solder joints. The coating and printing method is used to realize the uniform coating of the Ag paste on the micro Cu pillars, and the thickness of the coated Ag paste can be controlled. During flip-chip bonding, different power, pressure, temperature, and bonding time will affect the shear resistance of the solder joint after bonding. Therefore, this article controls the above factors and only studies the impact of ultrasonic power and pressure on the shear force of the solder joint interface. The experiment found that before reaching the maximum shear force, as the ultrasonic power increases, the shear resistance of the solder joint also gradually increased. After that, as the ultrasonic power increased, the shear resistance of the solder joints gradually decreased. It shows that when using thermosonic flip-chip technology for chip bonding, the ultrasonic power should be maintained in an appropriate range to make the bonded flip-chip solder joints obtain a maximum shear strength. The bonding pressure is proportional to the shear strength of the solder joint. [ABSTRACT FROM AUTHOR]

The current trend of electrical devices development is progressing towards miniaturization, multi-function and high density, device integration and fine pitch in a smaller package size. This led to the invention of copper pillar bumps which acts as a connection between the dies to its corresponding substrate, which allows the fabrication of smaller semiconductor devices. The dies were mounted onto the substrate by undergoing mass reflow process where the SAC305 solder from the copper pillar bumps and substrate bumps will melt together and solidify to form a solder joint. The quality of the solder joint is influenced by the parameters that govern the reflow profile, which are ramp rate, soak time, time above liquidus time, peak temperature and cooling rate. If the reflow profile is not properly optimized, defects such as voids in the solder joint can pose a reliability issue for the packaged unit. Therefore, in this paper, ramp rate, soak time and time above liquidus of reflow profiles for die utilizing copper pillar bumps with SAC305 as its solder material was studied and optimized in finding the recommended range of each parameter of the reflow profiles that yield the least voiding in the solder joint. The experiment was conducted by varying the reflow profile parameter which are ramp rate, soak time and time above liquidus, which the solder joint cross section and X-ray images were then analysed to study its influences. Additional experiment that investigates flux outgassing rate of different flux activity levels and the influence of component standoff height and mis-alignment offset towards solder-creeping defect were conducted in this article. [ABSTRACT FROM AUTHOR]

An electret refers to a permanent electric dipole. Nonconductive electrets (polymers and ceramics) have long been studied and utilized, but conductive electrets (metals and carbons) are emerging. This paper introduces the concept of the electret-based capacitance C′ to elucidate the discharge behavior of conductive electrets in the form of unpoled solder and other conductors (metals). The C′ is defined as the electret charge Q′ (determined by integrating the discharge curve) divided by the DC electret voltage V′. The conventional permittivity-based capacitance C (measured) is lower than C′ by orders of magnitude. For Sn–4Ag lead-free solder, C′ (given by Q′/V′) is 620 F, whereas C is 175 pF. The electret stems from the interaction of a small fraction of the carriers (free electrons) with the atoms, as supported by DC polarization asymmetry. For Sn–4Ag, this fraction is 3.5 × 10–9. Electret discharge (V′ decreasing to zero) occurs upon short circuiting. Self-charge (V′ restored) occurs upon subsequent open circuiting, being slightly more sluggish than discharge. The electret discharge/charge amounts to discharge/charge of C′. The discharge/charge time constant is found to approximately equal RC′ (R = resistance) and the discharge/charge energy is found to approximately equal ½ C′V′2, as expected for the discharge/charge of C′ and shown for Sn–4Ag, copper (0 and 37% cold work) and low-carbon steel. This two-fold agreement between theory and experiment for each of the metals studied strongly supports the C′ concept. Strong correlation occurs among high fraction of carriers that participate, high participating charge density and high discharge time constant. [ABSTRACT FROM AUTHOR]

The expanding market scale of the insulated gate bipolar transistor as a new type of power semiconductor device has higher insulated gate bipolar transistor soldering requirements. However, there are some small bubbles difficult to detect. The accuracy and speed of existing detection algorithms are difficult to meet the requirements of automated quality monitoring. For solving these problems, a detection data set of solder layer images captured by X-ray and labeled was made and an improved algorithm based on YOLOv5 was proposed, which can detect defects accurately and at a fast speed. The main contributions of this research are as follows: (1) a tiny bubble detection layer that further integrates the deep feature information and shallow feature information is added to improve the model's ability to detect small bubbles; (2) to speed up model convergence by optimizing anchor frame parameters; (3) we change the EIoU loss function as the bounding box loss function to solve the sample imbalance of the dataset; (4) combine the Swin Transformer structure to improve the convolution module and form a new feature extraction module, and introduce it into the backbone layer to improve the detection accuracy. The results of the experiment show that the overall performance of the improved network is better than the original and mainstream detection algorithms. The accuracy of the improved YOLOv5_SEST has reached 94.5% and 5.6% improvement in mAP for common bubble defect detection compared to the original algorithm. Our model size is only 5.3 MB, and the detection speed reaches 110 f/s. Therefore, the improved YOLOv5_SEST can well meet the requirements of automated quality monitoring of insulated gate bipolar transistors. [ABSTRACT FROM AUTHOR]

Purpose: This study aims to study the mechanical, photoelectric, and thermal reliability of SAC307 solder joints with Ni-decorated MWCNTs for flip-chip light-emitting diode (LED) package component during aging. By adding nanoparticles (Ni-multi-walled carbon nanotubes [MWCNTs]) to the solder paste, the shear strength and fatigue resistance of the brazed joint can be improved. However, the aging properties of Ni-modified MWCNTs composite solder joints have not been deeply studied. In this research, the mechanical, photoelectric and thermal reliability of SAC307 packaged flip-chip LEDs with Ni-MWCNTs added during aging were studied. Design/methodology/approach: Compared with SAC solder alloys, the effects of different contents (0, 0.05, 0.1 and 0.2 Wt.%) of Ni-MWCNTs on the photoelectric and thermal properties of composite solder joints were examined. To study the aging characteristics of composite solder joints, the solder joints were aged at 85°C/85% relative humidity. Findings: The addition of an appropriate amount of reinforcing agent Ni-MWCNTs reduces the density of the composite solder to 96% of the theoretical value of the SAC solder alloy. In addition, the microhardness increases and the wetting angle decreases. Two different phase compositions were observed in the solder joints with Ni-MWCNTs reinforcement: Cu3Sn and (Cu, Ni)6Sn5. The solder joints of SAC307-0.1Ni-MWCNTs exhibit the highest luminous flux and luminous efficiency of flip-chip LED filaments, the lowest steady-state voltage and junction temperature. And with the extension of the aging time, its aging stability is the best. In short, when the addition amount of Ni-MWCNTs is 0.1 Wt.%, the solder joints exhibit the best wettability and the thinnest intermetallic compound layer. And the shear strength of the tested solder joints is the best, and the void ratio is the lowest. At this time, the enhancement effect of Ni-MWCNTs on the composite solder has been best demonstrated. Research limitations/implications: The content range of enhancer Ni-MWCNTs needs to be further reduced. Practical implications: The authors have improved the performance of Ni-modified MWCNTs composite solder joints. Originality/value: Composite solder with high performance has great practical application significance for improving the reliability and life of the whole device. [ABSTRACT FROM AUTHOR]

Copyright of Przegląd Elektrotechniczny is the property of Przeglad Elektrotechniczny and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper reviewed the state-of-art copper pillar technology in flip-chip packaging, driven by the semiconductor industry's demands for thinner and faster data transmission. This technology with area array feature is a surface mount technology process used to form interconnection bonding between ball grid array chip and printed circuit board (PCB) by the reflow soldering process. The conversion of the flip-chip interconnection bump from the solder ball to the Cu pillar bump with the solder cap and the joint performance within the reflow oven are presented in this review. The simulation tools have recently facilitated the Cu pillar bump research during the PCB assembly process. Thus, this review focuses on the simulation modeling of the PCB assembly within a reflow oven using different numerical approaches. The thermal and air flow aspects of the reflow process are reviewed. The temperature distribution and the thermal stress condition of the PCB assembly within the reflow oven are predicted to understand better the fluid–structure interaction in the reflow oven. The considerations of air flow and thermal effects enhanced the study of fluid flow on the PCB assembly. Moreover, the Cu pillar technology challenges are also highlighted in this review. This review paper is expected to provide necessary information and direction to future researchers and industrial engineers when designing a brand-new surface-mounted component. [ABSTRACT FROM AUTHOR]

The combination of flexible-printed substrates and conventional electronics leads to flexible hybrid electronics. When fabrics are used as flexible substrates, two kinds of problems arise. The first type is related to the printing of the tracks of the corresponding circuit. The second one concerns the incorporation of conventional electronic devices, such as integrated circuits, on the textile substrate. Regarding the printing of tracks, this work studies the optimal design parameters of screen-printed silver tracks on textiles focused on printing an electronic circuit on a textile substrate. Several patterns of different widths and gaps between tracks were tested in order to find the best design parameters for some footprint configurations. With respect to the incorporation of devices on textile substrates, the paper analyzes the soldering of surface mount devices on fabric substrates. Due to the substrate's nature, low soldering temperatures must be used to avoid deformations or damage to the substrate caused by the higher temperatures used in conventional soldering. Several solder pastes used for low-temperature soldering are analyzed in terms of joint resistance and shear force application. The results obtained are satisfactory, demonstrating the viability of using flexible hybrid electronics with fabrics. As a practical result, a simple single-layer circuit was implemented to check the results of the research. [ABSTRACT FROM AUTHOR]

The undesirable impacts of solder void defects on the reliability of die packages have prompted stringent requirements on solder void size control in the semiconductor packaging industry. Vacuum reflow process using Pb95Sn5 solder was studied, where critical process parameters within temperature and pressure profiles were varied for enhanced solder void size reduction, in comparison to conventional reflow process. Higher reflow temperature profile, faster pressure pump-down rate, and longer vacuum dwell time above threshold levels are critical conditions required for consistently achieving minimum solder void sizes well below the industry criteria. Application of threshold conditions using large volume reflow oven with industrial settings has achieved the single and the total solder void size over die size well below the standard 2.5% and 5% requirements, respectively, with majority of the samples attained the single and the total solder void size over die size below 1% and 2%, respectively. Solder bond line thickness exhibited a significant influence on the solder void size reduction and thus needs to be administered appropriately during die packaging assembly to achieve the maximum solder void size reduction. [ABSTRACT FROM AUTHOR]

The heat source based on the self-propagation reaction of Al/Ni thin foil has the characteristics of concentrated heat, fast temperature rise/fall rate and small heat-affected zone; it can complete the melting and solidification crystallization of solder within milliseconds to realize solder interconnection, which can solve the problems of damage to heat-sensitive materials and components caused by monolithic heating of package structure. However, due to the highly non-stationary interconnection process, the resulting microstructure morphology may affect the service performance of the interconnected joints. In view of this, to investigate the post-solder microstructure of solder based on the self-propagation reaction, this paper analyzes the effect of the initial microstructure on the post-solder microstructure by heating 300-μm-thick SnBi solder with a 40-μm Al/Ni thin foil. The results indicated that the short melting time could resulted in the incomplete melting of heterogeneous phases and the non-uniform distribution of elements during the melting process, which had a significant effect on the morphology and composition distribution of the solidified microstructure, as well as the hardness distribution of the melted zone. The above conclusions have the potential to improve the interconnection process based on the self-propagation reaction, which is critical for both theoretical guidance and engineering application. [ABSTRACT FROM AUTHOR]

The mechanical and fatigue properties of microelectronic interconnection materials are important issues in critical applications in the life of electronic assemblies. Due to the growth in the applications of electronic components in new technological products used in tough conditions, evaluating the reliability of solder alloys has become crucial to the prediction of product life. SAC (Sn-Ag-Cu) solder alloys are common lead-free alloys used to form solder joints. In the current study, the reliability of individual SAC305 solder joints in actual setting conditions with an organic solderability preservative (OSP) surface finish was examined using an accelerated shear fatigue test at different load levels (16 MPa, 20 MPa, and 24 MPa). Four operating temperature levels (−10, 25, 60, and 100 °C) were also used. Seven samples were utilized at each experimental condition. An orthogonal array (L12) was employed for this experiment. The fatigue behavior of the SAC305 solder joints in actual setting conditions was described by a two-parameter Weibull distribution. The characteristic life and the shape parameter were extrapolated from the Weibull distribution for each experimental condition. Characteristic life was employed to represent the fatigue resistance of the solder joints. For each sample, the inelastic work per cycle and plastic deformation were determined. The results indicated a notable increase in the inelastic work per cycle and the plastic strain as a result of increasing either the stress load or the working temperature. Combinations of stress amplitude, working temperature, inelastic work, and plastic deformation were applied as inputs to the fuzzy system for computing a comprehensive output measure (COM-Value) using the Mamdani method. A negative relationship was observed between the solder life and the four fuzzy inputs. To fuzzify the inputs of the fuzzy system, two membership functions, "MFs", were formed for each input, and five MFs were set for the output. The center-of-gravity (COG) theorem was utilized as a defuzzification method in the fuzzy inference system. The characteristic life of the solder joints was predicted by the COM-Value, which was used as an independent variable. Finally, The COM-Value was used to generate a general predicted reliability model for SAC305 solder joints with an acceptable model adequacy index. [ABSTRACT FROM AUTHOR]

Lately, as electronic devices are continually becoming smaller, thinner, and multifunctional, there has been a growing demand for highly integrated packaging technologies. Accordingly, the application of flip-chip bonding technology has significantly increased to meet these demands. Therefore, the reliability evaluation of the micro-sized solder bumps used in flip-chip bonding and an understanding of the relevant mechanical properties has become essential. To evaluate the properties and reliability of Sn–2.3Ag (in wt%) flip-chip bump in various environments, this study compared the results of shear tests performed under three varying conditions, viz., shear heights (10, 15, 20, and 25 μm), shear rates (50, 100, 150, 200, 300, and 500 μm/s), and shear temperatures (25, 50, 100, 125, and 150 °C). A global bond tester was used for the shear tests and scanning electron microscopy was used to observe and analyze the fracture surfaces and joint cross sections subsequent to the tests. The experimental analysis showed that the shear test conditions had a significant impact on the shear strength and joint mechanical properties of the flip-chip bumps. The shear strength tends to decrease as the shear height and temperature increase, whereas it tends to increase in correspondence with increase in the shear rate. The correlations between the results of the mechanical characterization according to these test conditions were comparatively analyzed. [ABSTRACT FROM AUTHOR]

This paper investigates the influence of the welding process on the microstructure and mechanical properties of Au/Sn–3.0Ag–0.5Cu/Cu solder joints. In this study, the flip-chip LED chip and the substrate were connected by a heating platform, hot air reflow, and vacuum reflow soldering methods to form Au/Sn–Ag–Cu/Cu composite solder joints. Sn–3.0Ag–0.5Cu is selected as the solder. The microstructure of the solder joint interface and the inferred surface is studied to characterize the influence of different welding methods on the intermetallic compound (IMC) interface. The void ratio of the flip-chip solder layer was tested to characterize the effect of the effective connection area between the chip and the solder joint on the shear strength. The experimental results show that the void ratio of the solder joints welded by the heating platform is as high as 26%, the IMC interface thickness is higher, and the diffusion coefficient of the solder is the lowest. The void distribution of hot air reflow soldering joints is relatively uniform, and there is less solder residue on the fractured surface. Vacuum reflow soldering has the lowest void rate in the solder joints, and the solder joints have flat cross sections with almost no solder residues. The fracture occurs at the lower layer of solder. Considering comprehensively, when the soldering method is vacuum reflow, the IMC layer of the flip-chip solder joint is the thinnest, and the diffusion coefficient of the solder is the highest. There are almost no voids in the solder layer, and the mechanical properties of the solder joint are the best. At this time, the photo-thermoelectric parameters of the filament are the best, and the performance is the most stable and reliable. [ABSTRACT FROM AUTHOR]

High entropy alloy (HEA) receives noticeable attention in the electronic industry, and one of the best ways to incorporate HEA with the existing assembly setup is to reinforce HEA particles in Pb-free solder. This paper investigates the properties of Sn3.5Ag0.5Cu (SAC 305) solder reinforced with HEA particles. FeCoCrNiCu particle was synthesized via ball milling and dispersed in SAC 305 paste by powder mixing technique. DSC analysis confirms a reduction in melting temperature and undercooling with the addition of HEA. The dispersion of HEA in the solder resulted in a significant refinement in β-Sn grain size, Ag3Sn, and Cu6Sn5 IMC particle size. Also, SAC 305 with 0.2 wt% HEA noted a better spreading performance and lowest contact angle. 1608 chip capacitor/HEA reinforced solder joint was assembled, subjected to − 40 to + 125 °C thermal shock, and tested for the shear strength. The reliability analyzed through Weibull analysis showed a 30% increase in the 75% survival probability strength for HEA-added joints. Also, HEA addition till 0.1 wt% suppressed the growth of (Cu, Ni)6Sn5 IMC after thermal shock cycles. After 1000 thermal shock cycles, 0.1 wt% HEA-added solder retained the shear strength of 22.5 MPa, equivalent to the strength exhibited by the SAC 305 in the as-reflow condition. [ABSTRACT FROM AUTHOR]

In order to control the interfacial intermetallics of the commonly used soldering joint in the electronics packaging products, copper and nickel-plated copper were selected as the substrates, SAC305 was selected as the solder, and a series of experiments were conducted. The pure copper was plated with nickel and then the nickel-plated copper substrate was heat-treated before reflow soldering. Effects of substrate heat treatment on reflow soldering and aging of the soldered joints were studied. The results show that the heat treatment of nickel-plated copper substrate before reflow soldering can enhance the adhesion between the substrate and the plated coating and it can inhibit the growth of interfacial intermetallic compound (IMC). In the aging process, the IMC layer thickness of the soldered joint without heat treatment on the substrate before reflow is thicker than that of the soldered joint with heat treatment before reflow. The IMC growth rate of the interfacial layer of the soldered joint without heat treatment on the substrate before reflow is 5.854 × 10–17 m2 s−1; the IMC growth rate of the interfacial layer of the soldered joint with the substrate heat-treated before reflow soldering is 3.193 × 10–17 m2 s−1. In the shear test, the shear strength of the solder joints with heat treatment on the substrate before reflow soldering is higher than that of the solder joints without heat treatment before reflow soldering. [ABSTRACT FROM AUTHOR]

Electronic devices need to work at high temperature in some fields for a long time, peculiarly step soldering technology, primary packaging and flip–chip connections, etc., along with the application of electronic products more and more widely. These phenomena promote the further development of high-temperature solders. Because of the high melting temperatures of Sn-Ag and Sn-Sb, they are suitable for high-temperature fields such as automotive electronics and avionics. In this review, the influences of trace elements and nanoparticles on microstructure, intermetallic components (IMC) growth, mechanical properties, wettability, melting behavior, and creep behavior of Sn-Ag and Sn-Sb solders have been summarized systematically. It was found that the addition of trace elements or nanoparticles into solders to be beneficial in improving the performance of Sn-Ag and Sn-Sb solders. Besides, the melting behavior of the solder at high temperatures can be further improved if Sn-Ag and Sn-Sb are used better as high-temperature solders. [ABSTRACT FROM AUTHOR]

In this work, we study the Transient Liquid Phase Bonding (TLPB) for flip chip interconnexion using copper pillar and SnAg solder alloy technologies. Cu and SnAg bumps with a size of 90 × 90 µm2 were deposited using electroplating process with a thickness of 20 µm and 15–30 µm, respectively. Two types of Cu were deposited: with or without additives. Before the TLPB process, soldering experiments with or without pre-reflow were carried out at 250 °C in order to insure a good filling of the joint. Afterwards, isothermal holdings up to 4 h were performed in the temperature range between 250 and 350 °C under air atmosphere. Two main aspects of Cu/SnAg system are studied and analyzed: (i) the evolution of morphology, microstructure, and growth kinetics of intermetallics (IMCs) during the TLPB and especially (ii) the formation and growth of gas bubbles within the liquid solder during TLPB process. Destructive (scanning electron microscopy) and non-destructive (X-ray) characterizations are performed to analyze and understand the evolution of microstructure as well as the formation and evolution of cavities within the joint during the TLPB process. Non-destructive X-ray radiography with 5 µm resolution and 3D X-ray tomography analysis with 0.7 µm resolution were conducted for the same joint at different steps of its evolution between its initial state (just after the soldering process: about 3 min at 250 °C) and 4 h at 250 °C in order to follow "in situ" the evolution of volume defects inside the joint and especially the evolution of gas bubbles within the joints. [ABSTRACT FROM AUTHOR]

The effect of Ni on the gold embrittlement in the Sn/Au/Ni solder bump was studied in this paper. The mechanical properties of (Au1−x,Nix)Sn4 (x = 0, 0.25, 0.5) bulk, β-Sn/(Au1−x,Nix)Sn4 interface and Ni3Sn4/(Au1−x,Nix)Sn4 interface were calculated based on first principles, respectively. For bulk (Au1−x,Nix)Sn4, the ratio between bulk modulus and shear modulus shows that the addition of Ni into bulk AuSn4 would increase the brittleness, which could lead to bulk gold embrittlement. For the (100) β-Sn/(080) (Au1−x,Nix)Sn4 interface, the introduction of Ni into AuSn4 would increase the adhesion energy of interface, indicating strengthening the interface. While for (111) Ni3Sn4/(080) (Au1−x,Nix)Sn4 interface, the inclusion of Ni into AuSn4 would decrease the adhesion energy and deteriorate the bonding strength of interface. Furthermore, the cracks are prone to initiate at the (111) Ni3Sn4/(080) (Au1−x,Nix)Sn4 interface in the ideal tensile simulation, indicating that the introduction of Ni into AuSn4 would cause the interfacial gold embrittlement, which is usually not concerned in previous theoretical studies. [ABSTRACT FROM AUTHOR]

The main purpose of this paper is the analysis of the electrical resistivity of solder joints depending on various surface finishes and on the number of reflow processes. The electrical resistivity was determined after 1, 2, 3, 5 and 6 reflow cycles as a replacement for the basic accelerated aging test. In this article, various surface finishes are compared by measuring electrical resistivity of solder joints between two soldering pads. The influence of standard surface finishes (ENIG, Lead HASL, Lead-free HASL, Cu, ImSn) with the new developed surface finish based on SnAg7 is also compared. Measurements show that the electrical resistivity is dependent on surface finish type and the thickness of the solder joint. The results prove that the new developed surface finish based on SnAg7 is stable against multiple reflows and comparable to the surface finish based on Au. The new developed surface finish based on SnAg7 can be recommended as a replacement for other conventional surface finishes. [ABSTRACT FROM AUTHOR]

In the actual production process, soldering is a key step in the flip-chip packaging process. The reliability of the interconnection interface of flip-chip LED chips is considered to be one of the most important reliability issues. This paper studies the influence of different soldering temperatures on the microstructure and shear behavior of the Au/Sn-3.0Ag-0.5Cu/Cu solder joints of flip-chip LED chips. The lead-free solder Sn-3.0Ag-0.5Cu was selected as the solder. The microstructure of the intermetallic compound (IMC) interface and the inferred surface of the solder joint is observed, and the microstructure evolution of the solder joint is analyzed. The void ratio of the solder joints at 250°C, 260°C, 270°C, 280°C, and 290°C soldering temperature was tested to characterize the influence of the contact area between the chip and the solder joint on the shear stress. In addition, the solder joints were aged for 1000 hours in an environment with a relative humidity of 85°C/85%, and a shear test was performed to evaluate the influence of the interface reaction on the mechanical reliability of the solder joints during the isothermal aging process. The research show that when the soldering temperature is 270°C, the Au on the bottom of the chip, and the solder and Cu on the substrate have fully reacted, and the solder joints have high shear resistance. The shear strength of the aging solder joints increases first and then decreases, because the high temperature repairs the defects in the solder layer caused by the low soldering temperature to a certain extent. With the extension of aging, cracks and voids gradually appear at the fracture interface, and the effective contact area decreases. The shear strength of the solder joint decreases, and the fracture mode becomes brittle. [ABSTRACT FROM AUTHOR]

SnBi lead-free solder is widely applied in the field of low-temperature soldering due to its excellent creep resistance, relatively low melting point (139 °C) and cost. However, the frangibility and poor ductility of the SnBi low-temperature solder limits its application in the field of electronic packaging. In this paper, the research progress and development direction of SnBi low-temperature lead-free solder are discussed. To promote the application of SnBi solder, the melting characteristics, wettability, microstructure, tensile properties, shear properties, creep properties and interfacial reaction of SnBi solder are analyzed and introduced systematically. It provides an important reference of understanding the current development of SnBi solders. [ABSTRACT FROM AUTHOR]

The electrical conduction behavior of solder is well-known, but the dielectric behavior has been reported only recently. Water in the environment commonly affects electronics performance. This work provides the first study of the effect of water on the dielectric behavior of solder (along the solder bar axis). It also provides the first report of a mixed dielectric, which is a new concept referring to the combination of an electronic dielectric and a molecular dielectric. The mixed dielectric here is a combination of Sn-4Ag solder (an electronic dielectric with relative permittivity 3.24 × 106) and water (a molecular dielectric with relative permittivity 80). In this mixed dielectric, the electric field from the high-permittivity solder promotes the electric field in the low-permittivity water, so the relative permittivity of the solder-water combination exceeds that of the corresponding solder-air combination. The relative permittivity of the combination decreases with decreasing solid (solder) volume fraction. For the highest water/air volume fraction in the combination, corresponding to the lowest solid volume fraction of 0.937, the replacement of air with water increases the relative permittivity at 100 kHz by 1.3%, from 3.09 × 106 to 3.13 × 106. The measured relative permittivity is higher than the corresponding calculated value based on the Rule of Mixtures, due to the fringing electric field associated with the water or air, which is not as able as the solder in trapping the electric field in the capacitance measurement using coplanar electrodes. [ABSTRACT FROM AUTHOR]

The demand for miniaturised electronic devices has led to various challenges in microelectronic industries. One of the challenge is the removal of fans in some applications, which has led to increased heat retention, thereby causing overheating. In the assembly of electronic devices, thermal interface materials (TIMs) can be used for bonding the surface between the flip chip and a heat sink base or heat spreader. Lead-free solder (Sn-Ag-Cu) alloys are becoming more popular as TIMs in electronic assembly. Therefore, these lead-free solders could fail during operation at elevated temperatures over a period of time. The reliability of lead-free TIMs is vital in sustaining the life span of an electronic device. Three Sn-Ag-Cu (SAC) solders were considered for this investigation, namely, SAC305, SAC105, and SAC396. An ANSYS design modeller was used in the design and analysis of the microelectronic application investigated. Temperature loads ranging between 100°C and 200°C were applied over a period of time during the simulation of the electronic package. The findings from the research suggested that the SAC305 solder TIMs will outperform SAC105 and SAC396 during operation. This is because SAC305 can accommodate more stress, while the strain rate is low compared to SAC105 and SAC396. In addition, the fatigue life of SAC305 was higher than that of SAC105 and SAC396 in the different temperature ranges investigated. Therefore, SAC305 is recommended as a better thermal interface material compared to SAC105 and SAC396. [ABSTRACT FROM AUTHOR]

An electret is a permanent electric dipole exhibited by a material. This work provides the first report of the electret behavior of a solder, which is Sn–4Ag in the form of a fluxless unpoled wire of diameter 2.79 mm. The electret voltage increases linearly with the inter-electrode distance l, due to Ohm's Law. The electret's electric field also increases with l, increasing by 2.8% upon increasing l from 100 to 1000 mm. The electret discharges upon short-circuiting (with the electric field decreasing to zero) and charges back upon subsequent open-circuiting (with the electric field fully restored). For l = 1000 mm, the voltage is 0.77 µV, the electric field is 0.77 µV/m, the current is 32 µA, the discharge/charge time is 45 s, and the fraction of valence electrons that participate is 3.5 × 10−9, which is much greater than the fraction of valence electrons that participate in the AC permittivity (up to 3.6 × 10−14, decreasing with increasing l), which is in turn much greater than the fraction of valence electrons that participate in DC-current-induced polarization (up to 5.4 × 10−21). The electret's electric field is lower for solder than previously reported copper or steel. The fraction of carriers that participate in the discharge is much smaller for solder than copper. The discharge time is shorter for solder than copper, but the discharge time per unit participating charge is longer for solder than copper. The microstructure is believed to primarily govern the electret behavior, though the resistivity affects the permittivity and discharge time. [ABSTRACT FROM AUTHOR]

The influence of the soldering temperature on the performance of flip-chip light-emitting diodes (FC-LED) filaments soldered with SAC0307 has been investigated. Scanning electron microscopy (SEM) images, void rates, shearing force, junction temperature, steady-state voltage, blue light luminous flux, and luminous efficiency were measured to characterize the filament performance. The microstructure of the fracture surface after shear failure of the FC-LED filament joints soldered at 250°C and 270°C showed the lowest percentage of voids and was smoother than for the other groups. The shearing force of the FC-LED filament solder joints formed at 250°C and 270°C was higher than that for the other three groups, but the shearing force of all five groups of solder joints exceeded 200 gf. The steady-state voltage and junction temperature of the 250°C and 270°C FC-LED filaments were lower than those of the other three groups, and the blue light luminous flux of the 250°C and 270°C FC-LED filaments was higher than for the other three groups. In conclusion, the FC-LED filaments exhibited good photoelectric performance and thermal reliability when using soldering temperatures between 250°C and 270°C. [ABSTRACT FROM AUTHOR]

Ferroelectric behavior is well known for nonconductive dielectrics. This work provides the first report of this behavior in a metal, specifically a solder (Sn–4Ag), which is highly conductive. As required for ferroelectric behavior, the polarization changes sign when the applied electric field changes sign. The curve of polarization vs. electric field over positive and negative values of the electric field is asymmetric, with the forward polarization being greater than the subsequent reverse polarization, regardless of the direction of the initial current (electric field), due to the hysteresis. A minimum electric field magnitude of 1 × 10−3 V/m (corresponding to an energy of 0.5 meV) is needed for the polarization magnitude to be nonzero. Above this value, the polarization magnitude increases with increasing field magnitude, with the slope of the curve increasing with the field magnitude, reaching a constant value when the field magnitude exceeds 4 × 10−3 V/m. The polarization does not level off, indicating the absence of saturation in the polarization, as expected from the polarization stemming from the free electrons interacting with the atoms. This is in contrast to nonconductive ferroelectric materials, which exhibit polarization saturation. The maximum slope of the curve gives the DC relative permittivity of 6.10 × 103, which is smaller than the AC permittivity based on capacitance measurement by three orders of magnitude. The ferroelectric behavior is potentially useful for data storage, voltage-based tuning of the capacitance and polarization polarity switching through the reversal of the polarity of the electric field. [ABSTRACT FROM AUTHOR]

Thermal compression bonding (TCB) has been widely used in flip chip bonding processes for three-dimensional integrated packaging. Therefore, studying the TCB process and solder joint structure is significant for improving reliability. In this study, a Ni layer was deposited between the Cu/Sn-3.5Ag solder bumps of upper and lower chips, and TCB process tests were carried out at different bonding temperatures, forces and times. The solder height at the top and bottom of the copper pillar were recorded. Through the establishment of a mathematical analysis model, the relationship between the solder joint height and maximum stress was analyzed theoretically, and the trend of the shear stress and solder joint height was obtained from die shear tests. Then, the solder joint morphology, strength and microstructure composition of the microbumps were observed after aging. Our results showed that the growth rate of intermetallic compounds (IMCs) for Cu/Sn-3.5Ag microbumps with a 25 μm diameter was 2.5 times those with a 100 μm diameter and that the Ni barrier layer prevented the diffusion of Cu in Sn-3.5Ag solder. In addition, the Ni layer improved the strength of the Cu/Sn-3.5Ag joints after aging. Finally, with extended aging time, the fracture site was found to move from the solder region to the Cu6Sn5 layer for the Cu/Sn-3.5Ag samples, while it remained at the Sn-3.5Ag/IMC interface for the Cu/Ni/Sn-3.5Ag samples. [ABSTRACT FROM AUTHOR]

Nanosilver paste, an interconnect solder, is a common choice in the electronic packaging industry; however, higher sintering temperatures and lower sintering strength limit its application. At present, core–shell nanoslurry has been studied and applied to chip interconnection. Based on the mechanism of heterogeneous flocculation, we have developed a new nanosilver wrapped tin paste (Sn@Ag paste), and according to the decomposition temperature of the organic dispersant in the slurry, a corresponding sintering process with a temperature of 300 °C was developed. The Sn@Ag core–shell structure makes Sn have good dispersibility and oxidation resistance, and the sintered product of the slurry is a mixture of a solid solution of Ag and an Ag3Sn phase. Among them, the hard and brittle phase Ag3Sn acts as a dispersion strengthening effect in the Ag matrix phase, and the solid solution of Ag acts as a replacement solid solution strengthening. With the increase of doping Sn content, the sintering strength is significantly improved. When the Sn content is 5%, the joint shear strength reaches the highest value of 55 Mpa, which is higher than the pure nanosilver paste by 10 Mpa. This new nanosilver wrapped tin paste technology has the characteristics of low-temperature sintering and high-temperature service. [ABSTRACT FROM AUTHOR]

Solder is widely used for electrical interconnections in electronics, and its use involves the melting and subsequent solidification of the solder. This paper reports for the first time the effect of the cooling rate in solidification on the electrical behavior (conduction and dielectric behavior) of the solidified solder. Prior work addressed the effect of the cooling rate on the microstructure and mechanical properties only. The solder is Sn-4Ag (lead free, melting temperature 221 °C). Cooling is from the melt at 230 °C. Comparison of the cooling rates corresponding to air cooling and ice-water quenching indicates that the microstructure is much finer and the resistivity (DC) is higher by 2.4% for the quenching case. However, the permittivity (100 kHz) is the same for the two cooling rates. This means that the microstructural refinement associated with the quenching decreases the mobility without affecting the carrier–atom interaction responsible for the permittivity. The carriers are the valence electrons. Since the polarization associated with the permittivity involves the interaction of a fraction of the valence electrons with the atoms, this further implies that the fraction of carriers that interact with the atoms is not affected by the microstructural refinement and that the decrease in mobility (as indicated by the resistivity increase) does not affect this fraction. The fractional increase in the resistivity due to the quenching (relative to air cooling) during solidification (this work) is small compared to that due to the mild heating of the solid solder to 70 °C (our prior work). The mild heating also does not affect the permittivity. [ABSTRACT FROM AUTHOR]

This paper investigates the effect of soldering temperature on solder joint voids and reliability of flip-chip LED chips during reflow soldering. Lead-free solder SAC305 was used as solder paste. The void ratio of the flip-chip LED solder joint at 250°C, 260°C, 270°C, 280°C, and 290°C reflow soldering temperatures was detected by x-ray detector. Shear tests were conducted to evaluate the influence of interfacial reactions on the mechanical reliability of solder joints. The distribution of voids in the shear section was observed by scanning electron microscope (SEM). Next, the photoelectric and thermal properties of FC-LED filament were tested and analyzed. Finally, a high-temperature and high-humidity aging experiment was carried out to test the reliability of the LED filament. The results show that the void ratio of the LED filament soldering joint is the lowest when the soldering temperature is 270°C. The small void ratio of the solder joints results in lower steady-state voltage and junction temperature of the flip-chip LED filament. As the void density in the solder joint decreases, the shear strength of the solder joint increases. At this time, the shear resistance and mechanical reliability are the highest. [ABSTRACT FROM AUTHOR]

This work provides the first report of the effect of the dielectric behavior on the conduction behavior of solder. The lead-free solder studied contains 96 wt% tin and 4 wt% silver. The electric polarization stems from the interaction of the valence electrons with the atoms. The fraction of valence electrons that participate in the initial polarization is of the order of 10–9. The injected electrons play a minor role compared to the valence electrons of the solder in the polarization. The efficiency of the injected electrons in promoting the polarization decreases with the increasing number of injected electrons. Due to the polarization under a constant applied DC current (30–100 mA), the apparent electrical resistivity increases beyond the true resistivity. The rate of apparent resistivity increase diminishes as the time of current application increases. The fractional increase is 0.10% at 130 s of 100-mA current application. The higher is the current, the greater are the degree and rate of polarization at a given time. The current effect saturates above ~ 90 mA. Upon reversal of the polarity of the applied current, depolarization (followed by reverse polarization) occurs. The rates of depolarization and reverse polarization, as indicated by the rate of apparent resistivity increase, increase with increasing current. These rates decrease with increasing time. At the same current and respective time, the rates of polarization and depolarization are essentially equal, but the rate of reverse polarization is much below that of the initial polarization. Furthermore, the nearly saturated degree of reverse polarization is much below that of the initial polarization. This indicates a partially irreversible effect of the initial polarization that hinders the reverse polarization. [ABSTRACT FROM AUTHOR]

The influence of Al2O3 nanoparticles addition in trace amounts and electroless Ni–P substrate coating on the microstructure development and bond shear strength of Sn-3.0Ag–0.5Cu (SAC305) solder joint were investigated. The performance and reliability of the 2220-capacitor joints with Al2O3 nanoparticle reinforced nanocomposites reflowed on Cu and Ni–P coated substrate were analyzed under varying high-temperature environments. The addition of nanoparticles enhanced the wettability and microhardness of the solder and considerably refined the joint microstructure. The dispersion and adsorption of Al2O3 nanoparticles resulted in the suppression of intermetallic (IMC) growth at the interface and refinement of the β-Sn grains as well as IMC precipitates into the matrix. The Ni–P coating on the substrate significantly retarded the IMC growth kinetics resulting in the formation of a thin and uniform IMC layer at the joint interface. The thermal stability and performance of the joint under high-temperature environments were enhanced due to the Ni–P coating on the substrate. Compared to the unreinforced SAC305 solder joint with bare Cu substrate, joints with SAC305 + 0.05Al2O3 composite showed about 17% higher shear strength with bare Cu substrate and about 27% higher strength with Ni–P coated substrate. The Weibull distribution analysis indicates a significant improvement in joint reliability of the 2220-capacitor/SAC305 solder assembly using SAC305 + 0.05Al2O3 nanocomposite and Ni-coated substrate. The ANOVA study suggests that the solder joint performance majorly depends on the operating environment, solder composition, and the substrate finish. [ABSTRACT FROM AUTHOR]

Due to the increased complexity and optimization in microprocessor packaging from 2D to 3D packages, the size of solder joints is being reduced significantly. This trend currently leads to an increased amount of current density across flip-chip solder joints as well as microbumps and causes electromigration-oriented void formation and subsequent failure of the solder joints. It has been observed from literature that solder material undergoes microstructure evolution and subsequent degradation of mechanical properties under isothermal aging conditions. The current study is based on the effects of material property degradation due to thermal aging of flip-chip Sn-Ag-Cu (SAC) solder joints on electromigration-oriented failure. Finite element analysis has been used to analyze the diffusion characteristics of a SAC solder joint under isothermal aging conditions of 100°C for a period of 1–20 days, and electromigration simulation has been performed at two different temperatures of 100°C and 125°C for 100 h at an input current range of 0.01–0.05 A. The effect of intermetallic compound (IMC) layer thickness is analyzed to reveal the impact on electromigration-oriented failure in isothermally 60 days long aged solder bumps. Results have revealed that resistance to electromigration-oriented failure is higher in the case of aged components compared to unaged components along with the increment of time to failure with IMC formation in the SAC solder joint. [ABSTRACT FROM AUTHOR]

Purpose: This paper focuses on the reliability of the solder joint after the self-alignment phenomenon during reflow soldering. The aim of this study is to analyse the joint quality of the self-alignment assemblies of SnAg alloy solder joints with varying silver content. Design/methodology/approach: The shear strength assessment was conducted in accordance with the JIS Z3 198-7 standard. The standard visual inspection of IPC-A-610G was also performed to inspect the self-alignment features of the solder joint samples. Statistical analysis was conducted to determine the probabilistic relationship of shear strength of the misalignment components. Findings: The results from the mechanical reliability study indicate that there were decreasing trends in the shear strength value as misalignment offset increased. For shift mode configuration in the range of 0-300 µm, the resulting chip assembly inspection after the reflow process was in line with the IPC-A-610G standard. The statistical analysis shows that the solder type variation was insignificant to the shear strength of the chip resistor. The study concluded that the fracture occurred partially in the termination metallization at the lower part of the chip resistor. The copper content of the joint on that area shows that the crack occurred in the solder joint, and high silver content on the selected zone indicated that the fracture happened partially in the termination structure, as the termination structure of the lead-free chip resistor consists of an inner layer of silver and an outer layer of tin. Practical implications: This study's findings provide valuable guidelines and references to engineers and integrated circuit designers during the reflow soldering process in the microelectronics industry. Originality/value: Studies on the effect of component misalignment on joint mechanical reliability are still limited, and studies on solder joint reliability involving the effect of differing contents of silver on varying chip component offset are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the potential industry. [ABSTRACT FROM AUTHOR]

In this study, the effect of appropriate Nd addition on improving the high-temperature reliability of Sn-3.8Ag-0.7Cu (SAC387)/Cu solder joint after aging treatment was investigated. The interfacial microstructure of solder joint was refined with proper addition of Nd. This phenomenon could be explained as the adsorbing-hindering effect of surface-active Nd atoms which blocked the growth of brittle intermetallic compounds (IMCs) in the solder joint. Theoretical analysis indicated that 0.05 wt. % addition of Nd could distinctly decrease the growth constant of Cu6Sn5 IMCs and slightly decrease the growth constant of Cu3Sn IMCs respectively. The shear force of SAC387-0.05Nd/Cu solder joint was evidently improved compared with the origin solder joint. In addition, SAC387-0.05Nd/Cu solder joint maintained excellent mechanical property compared with SAC387/Cu solder joint even after 1440 h aging treatment. [ABSTRACT FROM AUTHOR]

In this study, the effects of electromigration on a solder/copper substrate due to temperature and current density stress were investigated. The copper–tin (Cu–Sn) film samples were subjected under a fixed current and various heating conditions (130 °C and 180 °C) and current densities (different cross-sectional areas). The micro-structural changes and intermetallic compound (IMC) formation were observed, and failure phenomena (brittle cracks, voids, bumps, etc.) on the structures of samples were discussed. The results showed that the IMC thickness increased as the temperature and current density increased. Moreover, it was found that the higher the temperature and current density was, the greater the defects that were observed. By adjusting the designs of sample structures, the stress from the current density can be decreased, resulting in reduced failure phenomena, such as signal delay, distortion, and short circuiting after long-term use of the material components. A detailed IMC growth mechanism and defect formation were also closely studied and discussed. [ABSTRACT FROM AUTHOR]

The mass reflow (MR) process is widely used in electronic packaging interconnection. However, the conventional MR process can cause thermal damage to components and requires a long process time. The laser-assisted bonding (LAB) process is considered as an alternative soldering process for overcoming these limitations due to its extremely fast process time and high thermal selectivity. The LAB process causes low thermal damage; hence, it can be used to fabricate flexible and stretchable applications. This study investigates the mechanical properties, microstructural variation, and intermetallic reaction between the SAC 305 solder and Cu electrodes. The mechanical properties are investigated using shear tests, while the microstructure is analyzed using scanning electron microscopy and X-ray scans. Furthermore, the reliability of the LAB- and MR-produced SAC 305 solders is assessed using a high-temperature storage test. As a result, the intermetallic compound layer is found to be considerably thinner, and the volume of voids in the solder matrix is lower in the LAB-produced solder than that in the MR-produced solder. The mechanical properties of the LAB-produced solders are enhanced by these microstructural advantages. [ABSTRACT FROM AUTHOR]

A new three-dimensional finite element model to characterize the residual stress distribution in multilayer NTC thermistor during soldering process has been developed. During the soldering process, the effects of inner silver electrode number and lateral margin length on mechanical residual stress are studied. Throughout the weldbonding and heating process, the maximum and minimum principal stresses in the active region of the thermistor ceramic are not zero, which implies that most of the thermistor ceramic is not stress-free. Numerical results show that the increasing of the lateral margin length could effectively decrease the maximum tensile stress. [ABSTRACT FROM AUTHOR]

A conformal coating is a protective chemical material that can be applied as a thin layer on printed circuit board assemblies (PCBAs). The purpose of conformal coating is to prevent the interaction between external environmental factors and the electrical assembly. However, since conformal coating materials have different mechanical properties than electronic components, their use may induce additional mechanical stresses on the board. This study focuses on the effect of having a different coefficient of thermal expansion (CTE) for the conformal coating material from the solder joints of ball grid array (BGA) packages on printed circuit boards (PCBs). Typical lead-free solders have a CTE of less than 25 ppm/°C, while coating materials have a much higher CTE. For example, polyurethane has a CTE around 193 ppm/°C. This CTE mismatch generates stresses in different directions on the solder joints, especially when the assembly is subjected to temperature cycling during its service. In this effort, four samples of PCB assemblies that have BGAs were used in temperature cycling tests. The sample size is nine modules, with each module having at least 272 exposed BGA joints. Three of the samples were coated by a layer of polyurethane and one baseline sample was not coated. Coating thickness was selected to be the experimental design factor. Thus, these three samples, which had different thicknesses (30, 80, and $130~\mu \text{m}$), were evaluated and compared against each other and against the noncoated sample. By comparing the four samples, it was found that a thick coating material significantly reduced the lifetime for BGA solder balls by initiating early solder cracks, which propagated and caused complete separation in the solder joint. [ABSTRACT FROM AUTHOR]