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This research is to design an effective prefetching method required for hybrid main memory systems consisting of dynamic random-access memory (DRAM) and phase-change memory (PCM) components, which can be especially used for big data applications and massive-scale computing environment. Conventional prefetchers perform adequately for regular memory access patterns. However, graph processing applications show extremely irregular memory access characteristics, causing some difficulty in predicting accurate prefetching operation. Therefore, an effective dynamical prefetching algorithm based on the regression method is proposed in this study. We have designed an intelligent prefetch engine that can identify any dynamic accessing characteristics in memory accessing sequences. Specifically, it can select regular, linear, or polynomial regression predictive analysis based on the memory access sequence characteristics, and also dynamically determine the number of pages required for any selected prefetching. We also present a DRAM-PCM hybrid memory structure that can reduce the energy consumption and resolve the thermal issue that hampers conventional DRAM memory systems. Experimental results indicate that the performance can increase by around 40%, compared to that of conventional DRAM memory structures.

This research is to design a history table-based linear analysis method for a DRAM-PCM (phase change memory) hybrid memory system supporting irregular and complex memory accessing patterns in graph processing applications. This linear analysis method can analyze complex memory access patterns in real time through our history table structure, classifying address values requested from the LLC (last-level cache) as the prefetch candidates. Also, the proposed method is to support a prefetching operation from the storage onto the hybrid main memory, causing significant latency losses. Specifically, we proposed a new memory pattern analysis method, which is called a linear analysis based on a history table, to detect any linear memory access patterns from workloads showing irregular accessing characteristics. For the DRAM-PCM hybrid memory, dynamic data that are frequently accessed are stored in the DRAM. Thus, our linear analysis not only categorizes memory access patterns in the form of line patterns but also separates dynamic and static data so that the hybrid memory systems can be managed adaptively and efficiently. Our experiments show that our model can improve performance and energy consumption by 60% and 30%, respectively, compared to those of the traditional DRAM-only memory model. Moreover, our approach can enhance the entire system performance and energy consumption by 11.3%, 6.8%, compared to streamlined prefetcher-based models.

Biomedical and inertial sensors can be used to generate a complete view of complicated physiological changes in a continuous, real-time, and non-invasive manner. As inappropriate on-body attachments may result in errors, the localization information requires calibration. In most previous studies of on-body wearable device localization, the run-time performance was not evaluated in terms of execution time and memory usage. Recently, smartphones have been used as data processing centers and recognition systems for wearable devices. However, the hardware disadvantages of phone devices have a negative effect on both real-time response and system accuracy. In this study, we focus on a high-performance localization system for the mobile environment and propose a memory efficient algorithm that is accelerated by using graphics processing units (GPUs). The algorithm combines a k-nearest neighbor classifier with a support vector machine (SVM)-based decision-maker to refine the classification outcome. This contributes to a faster and more accurate on-body localization for wearable devices. Experiment results demonstrated that the proposed method achieves an accuracy of 92.94%% and is faster than Serial-SVM and GPU-SVM by a factor of 6.81×and 3.87×, respectively. Therefore, the proposed technique can offer a comparable accuracy to SVM-based methods with faster recognition in the mobile environment.

With the increasing complexity of graph structures, the current real-world large-scale graphs are being represented by a considerable amount of vertex and edge data. Furthermore, the analysis of a large number of computing nodes has become a very complicated job that requires a large amount of hardware resources. Moreover, in large-scale graph processing, the vertex and edge data show random and sequential memory access patterns at the same time, and this is a major bottleneck in graph processing. In this paper, we present a high-capacity main memory system with an intelligent pattern-aware prefetching engine to overcome the scalability problem and the memory inefficiency of single-machine graph processing. The proposed intelligent pattern-aware prefetching engine is designed to predict and handle sequential or regular patterns and random-access patterns simultaneously. Experimental results demonstrated that the proposed model exhibited performance improvements of 60% over conventional DRAM models, approximately 40% over the existing prefetch models, and about 12.5% over the latest prefetch models.

This research proposes a memory-disk integrated system (MDIS) with pattern analysis based data management method. The proposed system consists of a pattern adaptive prefetcher with DRAM-based dual buffers and a PCM-based persistent memory structure. The PCM-based persistent memory module is exploited as conventional main memory and storage layers simultaneously. In this system, to compensate the PCMs unfavorable characteristics, a pattern analysis based prefetching method by using dual DRAM buffers with a small amount of space are designed as a sort of caching layer. The proposed pattern analysis based data management method monitors the miss rate to determine the prefetch policy, e.g., when and what to prefetch. These schemes enable flexible adaptation to the application execution characteristics showing unpredictable and inconsistent workload patterns. In order to evaluate our system, we implemented a trace-driven simulator system and launched the YCSB on Redis, Apache Storm, Apache Spark, and OpenStack Swift. The experimental result shows that the MDIS with a pattern adaptive prefetcher can reduce the total access time by 13.9% compared to the conventional scheme and thus the overall performance of the memory-disk integrated system improves.

The amount of data is increasing explosively, and many in-memory-based database management systems have been developed to efficiently manage data in real time. However, these in-memory databases mainly use DRAM main memory, which raises problems due to price and energy consumption. To mitigate these problems, we propose a hybrid main memory structure based on DRAM and NAND flash that is cheaper and consumes less energy than DRAM. The proposed system incorporates a prefetching mechanism in last-level cache based on regression analysis to handle irregular memory access from the in-memory application and a migration technique based on clustering between DRAM and NAND flash to mitigate NAND flash slow access latency, which could otherwise significantly degrade system performance. We experimentally confirmed approximately 58% and 51% execution time and energy improvement compared with using DRAM alone. We also compared existing prefetching models without migration to evaluate the proposed prefetching and migration techniques and showed approximately 24% and 23% improvement for execution time and an energy consumption, respectively.

This article presents a novel prefetching mechanism for memory-intensive workloads used in large-scale data centers. We design a negative-AND-flash/dynamic random-access memory (DRAM) hybrid memory architecture as a cost-effective memory architecture to resolve the scalability and power consumption problems of a DRAM-based model. A smart prefetching mechanism based on a cluster-management scheme to cope with dynamically varying and complex access patterns of any given application is designed for maximizing the performance of the DRAM. In this article, we propose a new concept for page management, called a cluster, which prefetches data in our hybrid memory architecture. The cluster management is based on a self-learning scheme on dynamically changeable access patterns by considering any correlation between missed pages. Experimental results show that the overall performance is significantly improved in relation to hit rate, execution time, and energy consumption. Namely, our proposed model can enhance the hit rate by 15% and reduce the execution time by 1.75 times. In addition, we can save energy consumption by around 48% by cutting the number of flushed pages to about an eighth of that in a conventional system.

Owing to the exponential growth of real-time data generation, the importance of stream processing is ever increasing. However, the data processing paradigm of stream processing is quite different, so it is difficult to expect high performance from memory systems applied to existing data centers. To solve this problem, two main solutions are suggested in this paper. First, a hybrid main memory and small buffer architecture are designed to reflect the execution characteristics of stream processing. Second, a hardware-based prefetch module supports correlation prefetching. Stream processing tends to accept incoming data in the main memory, so the prefetch module is used to divert data from the main memory layer to the buffer layer based on an intelligent clustering algorithm. This clustering algorithm affects the rapidly changing data access pattern of stream processing applications. By using heterogeneous main memories, not only can one enjoy the fast access latency of DRAM but also its nonvolatility, scalability, and low power consumption. The proposed hybrid memory architecture with our prefetch buffer structure can improve the buffer hit rate by 9–14% over other prefetch methods, reduce energy consumption by 26% over the conventional DRAM-only model, and achieve similar execution time over the 1/8-size DRAM space of the DRAM-only model.

Owing to the increased need for machine learning and artificial intelligence in current cloud computing systems, the amount of data that needs to be processed has exponentially increased. Thus, it is important to optimize memory and storage systems to reduce the energy consumption and execution time of applications. This paper proposes a new Q-learning-based prefetching algorithm for DRAM---NAND flash hybrid main memory architecture. To minimize the computational overheads of learning-based schemes, we have designed two learning policies, namely aggressive learning and lazy learning. The proposed system reduces the energy consumption by about 80% of the memory and storage for Redis, OpenStack Swift which is a cloud computing open source framework and Apache Storm workloads. Further, the overall execution time of workloads in cloud computing applications is reduced by almost half. Using a path generator with a Q-learning-based prefetching algorithm, we realize an increased hit rate of about 21% compared to that with a no-prefetching system, compared to non-prefetching system.

This article proposes a new phase change memory– (PCM) based memory storage architecture with associated self-adaptive data filtering for various embedded devices to support energy efficiency as well as high computing power. In this approach, PCM-based memory storage can be used as working memory and mass storage layers simultaneously, and a self-adaptive data filtering module composed of small DRAM dual buffers was designed to improve unfavorable PCM features, such as asymmetric read/write access latencies and limited endurance and enhance spatial/temporal localities. In particular, the self-adaptive data filtering algorithm enhances data reusability by screening potentially high reusable data and predicting adequate lifetime of those data depending on current victim time decision value. We also propose the possibility that a small amount of DRAM buffer is embedded into mobile processors, keeping this as small as possible for cost effectiveness and energy efficiency. Experimental results show that by exploiting a small amount of DRAM space for dual buffers and using the self-adaptive filtering algorithm to manage them, the proposed system can reduce execution time by a factor of 1.9 compared to the unified conventional model with same the DRAM capacity and can be considered comparable to 1.5× DRAM capacity.

This paper presents a real-time lightweight fluid simulation based on a particle fluid technique developed for mobile environment . The Bullet physics engine and smoothed particle hydrodynamic (SPH) fluid algorithm will be used for our lightweight fluid simulation. First, we describe an advanced collision detection mechanism that will be used. By using this method, less computational resources are required. Secondly, we present a simplified SPH algorithm where nearby particles are grouped together to minimize the number of calculations. By decreasing the number of particles, an improved computational performance is expected. Finally, the ARM NEON based parallel computing technique was enabled to reduce execution time by lowering the number of arithmetic instructions. Several experiments are carried out where the experimental results indicate the first technique led to a 50% improvement in performance. The second technique provided a 17% overall improvement. The third technique delivered a performance improvement within the range of 26%–40%. Overall, the experimental results show that the proposed techniques provided an accumulative performance improvement of approximately 120% for all applied methodologies.

A new storage system that integrates non-volatile with conventional memory, a harmonized memory system (HMS) for object-based cloud storage, is proposed. The system overcomes IO bottlenecks when managing large amounts of metadata and transaction logs and is composed of five modules. The first, the harmonized memory supervisor, is a translation layer for accessing the harmonized array module. It manages address translation, address mapping by page linking, and wear leveling. The second, the harmonized array module, is divided into dynamic and static areas composed of DRAM, and PCM together with NAND flash memory, respectively. The harmonized memory migration engine and data pattern predictor, which anticipates future data flow, are designed to maximize the effectiveness of the PCM array area. The harmonized logging conductor processes the log between the PCM array and NAND flash areas. Experimental results show the total execution time and energy consumption of HMS is 5.77 faster and 4.27 times lower, respectively, than the conventional DRAM-HDD model for object-based storage workloads.

In mobile computing systems, the limited amount of main memory space leads to page swap operation overhead and data duplication in both main memory and secondary storage. Furthermore, SQLite write operations in mobile devices such as smartphones and tablet PCs tend to frequently overwrite data to storage, significantly degrading performance. Thus, this article presents a unified memory-storage structure that is optimized for mobile devices and blurs the boundary between the existing main memory layer and secondary storage layer. This structure can eliminate the conventional page-swap operations that cause significant performance degradation and support fast program execution time. The unified memory-storage structure consists of a dynamic RAM (DRAM) and phase change memory (PCM) -based dual buffering module, a hybrid unified memory-storage array consisting of DRAM and NAND Flash memory, and an associated unified storage translation layer devised for the memory address and file translation mechanism as a system software module. This hybrid array of non-volatile memories is formed as a single memory-disk integrated storage space that can be logically divided into static and dynamic spaces. Experimental results show that the overall performance of the hybrid unified memory-storage system with the buffering structure increases by around 13% and power consumption is also improved by 35%, compared to current mobile system.

Computational scientific applications tend to be very data I/O intensive, producing a large amount of data as the execution result. In this research, we propose a new storage system using next-generation non-volatile memory that is suitable for exa-scale computing systems. This storage system is called the Cloud Computing Burst System (CCBS) and is composed of a unified table management module, data scoring module, and CCBS storage. In particular, CCBS operates as a workload enlightened storage system using its own data scoring module. The CCBS storage architecture consists of PCM/NAND Flash arrays and a data migration engine. CCBS storage cannot only provide a scaling out feature, but also improve the overall performance of the storage system. In addition, by using new non-volatile memory array, many benefits, such as low energy consumption, density scaling, and high performance, can be achieved. We demonstrate the effectiveness of our proposed system by simulating the storage system using scientific benchmarking tool. Our data scoring algorithm can provide 7% more hit rate than other methods for CCBS. In addition, our proposed system has improved storage system speed by 1.64 times, compared with only NAND Flash conventional model.

This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

Augmented reality has been on the rise due to the proliferation of mobile devices. At the same time, object recognition has also come to the fore. In particular, many studies have focused on object recognition based on markerless matching. However, most of these studies have focused on desktop systems, which can have high performance in terms of CPU and memory, rather than investigating the use of mobile systems, which have been previously unable to provide high-performance object recognition based on markerless matching. In this paper, we propose a method that uses the OpenCV mobile library to improve real-time object recognition performance on mobile systems. First, we investigate the original object recognition algorithm to identify performance bottlenecks. Second, we optimize the algorithm by analyzing each module and applying appropriate code enhancements. Last, we change the operational structure of the algorithm to improve its performance, changing the execution frequency of the object recognition task from every frame to every four frames for real-time operation. During the three frames in which the original method is not executed, the object is instead recognized using the mobile devices accelerometer. We carry out experiments to reveal how much each aspect of our method improves the overall object recognition performance; overall, experimental performance improves by approximately 800 %, with a corresponding reduction of approximately 1 % in object recognition accuracy. Therefore, the proposed technique can be used to significantly improve the performance of object recognition based on markerless matching on mobile systems for real-time operation.

In this paper, a new method is proposed for recognizing rotated objects based on extracted feature points from the Harris corner detector using object corner points at real time in a mobile environment. With this proposed method, corner points can be rapidly extracted from the input image and object recognition can be conducted by comparing existing feature points. Color values for corner pixels in the feature points of rotated objects are generally varied in accordance with the degree of object rotation. The color values of the feature points are affected by the degree of rotated objects; therefore, there is a possibility that these values can be mixed with nearby pixel values. By analyzing the color values of the rotated pixels, we can extract feature points of rotated objects and use them for object detection to be effectively applied for rotated object detection. Although overall recognition rate is somewhat degraded, using the proposed object recognition with corner information of feature points makes it possible to execute in real time in mobile environments by reducing the amount of computation. Accordingly, this method can be applied to recognizing rotated objects, even in a mobile environment with limited computing capabilities. Experimental results show that the proposed method can provide approximately 96 % accuracy and high performance compared to other methods. Therefore, the proposed method can be adapted to recognize any rotated object with performance and accuracy.

For the ubiquitous computing environment, an important assumption is that all the components in any specific environment are connected with each other. With this assumption, we introduce an effective scheme to provide a personalized service based on Virtual Personal World (VPW). Virtual Personal World (VPW) which is a model focused on service continuity with specially designed components. Previous ubiquitous frameworks have been concerned with the location where a user is provided any specific service. However those questions above are not the most important problems anymore in VPW. It concentrates on the point whether the services are successive or not, wherever a user goes to any place. Services are not regarded as a sum of functions which is embedded on any objects in any certain place. We conceptually define a resource management scheme based on a unified form of the object which participates in service provision, so called virtual object (VO). Thus the service can be described as the sum of functions of VOs. With our resource management scheme, users can utilize their required object as VO wherever it is located. And also, for better utilization of VPW service, we introduce a novel form of profiles and service provision scheme based on the polymorphism. Our simulation result shows that the Ratio of VPW pure service time is 0.15 % higher than conventional location based service. And also the possibility that users can meet adequate service he wants raised 29 % in our proposed VPW environment.

Next generation non-volatile memory devices are promising replacements for DRAM and Flash memories for mobile devices because of their energy efficiency and non-volatile characteristics. In this paper, we propose a new memory hierarchy system for next-generation non-volatile memory devices that is called an integrated memory-disk (IM-D) structure. It can merge a conventional main memory layer and a disk storage layer into a single memory layer using Phase change memory (PCM) and Flash memories. The IM-D architecture, consisting of a dual buffering IM-D adapter to improve the limited endurance and latencies, an array of PCM/Flash hybrid memories, and an associated memory management module called the IM-D translation layer in the operating system, is designed to utilize the advantages of next-generation non-volatile memory devices and at the same time overcome some shortcomings, like the asymmetric read/write access latencies and limited endurance, of a conventional memory hierarchy system. In the IM-D architecture, we propose an array of PCM/Flash hybrid memories and a migration scheme to enhance the cost effective performance and to reduce access latency. Our experimental results show that the miss rate of the proposed IM-D adapter is reduced by 49 % as compared with the conventional memory module, and the write count is reduced by 60.15 %. In addition, the access latency of the IM-D storage is improved by 45.3 %.

As DRAM-based main memory becomes a dominant factor in the energy consumption and cost of any computer system, new non-volatile memory technologies have been proposed to replace DRAMs. For example, PRAM is emerged as a leading alternative for main memory technology. However, the access latency of PRAM is significantly slower than that of DRAM and an interfacing converter is required to at least partly alleviate this latency difference. The interfacing converter sits between PRAM-based main memory and the last level of cache memory. In this paper, we present a proposed dynamic adaptive converter and its management scheme for PRAM-based main memory. In addition to overcoming long access latency, it provides enhanced endurance. The adaptive converter is composed of an aggressive streaming buffer to make better use of spatial locality by dynamically varying fetch size, a write buffer to improve endurance limit, and an adaptive filtering buffer to better utilize temporal locality. Our experimental results show that we can reduce buffer miss rate by about 59%, compared with using a single buffer structure with same space. Our approach also hides PRAM access latency more effectively. It improves the number of superblocks pre-fetched from main memory by 25%. Therefore, the converter shows its effectiveness comparable to a case with larger buffer space, without expending the extra power.

Multimedia system-on-a-chip (SoC) platform designs nowadays are facing some conflicting issues regarding product development. One is induced by increasing design complexity and another is induced by decreasing time-to-market. Hence, designers are seeking a more efficient and reliable methodology in order to design complex multi-million gate SoC under such harsh conditions. In particular, the complexity of a generic pin control block in multimedia SoC which implements input/output (I/O) paths for off-chip communication has increased exponentially in recent years. Accordingly, the possibility of introducing human errors in designing such block has grown. Operation of generic-pin control block needs to be validated with a top-level RTL from the early stages of design, which correctly checks full-chip interface. However, generic-pin control block has inherent several design issues since function registers and multi-I/O paths are usually fixed in the relatively late stages of design. Also, the role of a generic pin control block that shares limited pins causes frequent changes in pin assignment. Therefore, current design approaches of a generic pin control block are no longer adequate to meet the challenges of design productivity, design reusability, and shorter time-to-market for design. And, this results in many possible human errors when using a traditional RTL description. As a response to this problem, this paper presents a design automation based approach to reduce the possibility of human errors. In the case study presented, we succeeded in auto-generating a generic pin control block in multimedia SoC platforms which has more than 300 general purpose I/O interfaces including both input and output, as well as 900 PAD pins. Ultimately, we reduced the amount of manual description for generating a generic pin control block by a whopping 97 %.

Most superblock-based NAND flash storage systems employ a high-speed write buffer to enhance their writing performance. The main objective is to bind data of adjacent addresses as much as possible in order to transform random data into sequential data, which then facilitates interleaving in the storage system. We have designed a new superblock-based buffer scheme for NAND flash storage systems that improves on traditional schemes. For buffer management, a series of lists need to be specified to monitor the dataflow changes in the current state of the buffered data and the NAND flash memory in order to maximize interleaving during the flush operation. Experimental results show that the proposed scheme achieves higher write speed performance in almost all configurations, with greater than 50% speedup in some cases. Our proposed flash-aware write buffer (FAWB) scheme achieves this higher write performance with a required buffer space of only 1/4th–1/8th that of other schemes, resulting in higher efficiency.

To enhance performance of flash memory-based solid state disk (SSD), large logically chained blocks can be assembled by binding adjacent flash blocks across several flash memory chips. However, flash memory does not allow in-place overwriting and thus the operations that merge writes on these blocks suffer a visible decrease in performance. Furthermore, when small random writes are spread over the disk address space, performance tends to be degraded significantly. We thus present a technique to manage random writes efficiently to achieve stable SSD performance. In this paper, we propose a pattern adaptive SSD structure, which classifies access patterns as either random or sequential. The structure primarily consists of a write cache and a flash translation layer that separates groups of writes by access pattern (S-FTL). Separately managing the two types of write patterns enables greater parallelism and reduces the cost of large block management, thus enhancing the performance of the proposed SSD. Simulation experiments show that the proposed pattern adaptive structure can provide 39 percent decrease in extra flash block erase overhead on the average, and write performance can be improved by around 60 percent, compared with a basic FTL applied to existing parallel SSD structures.

This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.

In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources of a graphics processor. Specifically, cache misses and dynamic branches can cause additional latencies and complicated management in these parallel architectures. To address this problem, we combine a systolic execution scheme with on-demand warp activation that handles cache miss latency and branch divergence efficiently without significantly increasing hardware resources, either in terms of logic or register space. Simulation indicates that the proposed architecture offers 25% better performance than a traditional SIMD architecture with the same resources, and requires significantly fewer resources to match the performance of a typical modern vector multi-threaded GPU architecture.

In ubiquitous computing environments, users want to discover the most appropriate service to support their tasks. Because the most appropriate service depends on user preferences and context, service discovery protocols should personalize results. A service discovery framework based on the virtual personal space (VPS)-that is, a virtual administrative domain of services managed for the user-aims to provide this personalization. In this framework, personal operating middleware embedded in a personal device manages a set of contextually close services in the user's VPS. An inference module supports this management. Laboratory evaluations show that the VPS framework helps users find high-quality, appropriate services.

In ubiquitous computing, the computing environment for a user is no longer a fixed computer, but a space that includes multiple heterogeneous devices that can change dynamically according to the user's situation. Managing the space is an essential part of ubiquitous computing because application services in this environment need to be adaptive to the users' current situation. However, previous approaches oversimplified the model of personal space and demonstrated some limitations in developing user-centric adaptive services. In this paper, we propose an effective personal space model, defined as virtual personal world (VPW), and a sophisticated method to manage personal spaces. The VPW represents a personal space by using a set of stateful elements and their relationships, which are denoted as virtual objects, services, and neighbors. The VPW provides expressive and accurate information for a particular user, thereby helping application services adapt their operations for the user dynamically. Our conceptual model is designed as personal operating middleware software that manages the user's VPW and provides application services. Experimental results show that the prototype system based on VPW has reasonable performance in running application services and managing personal spaces. We also found that the VPW model can increase the average user satisfaction rate by up to 40% compared to other models in our simulation environment.

This paper proposes a data cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative cache and 17kB stream caches, respectively.

As the complexity of 3D scenes is on the increase, the search for an effective visibility culling method has become one of the most important issues to be addressed in the design of 3D rendering processors. In this paper, we propose a new rasterization pipeline with visibility culling; the proposed architecture performs the visibility culling at an early stage of the rasterization pipeline (especially at the traversal stage) by retrieving data in a pixel cache without any significant hardware logics such as the hierarchical z-buffer. If the data to be retrieved does not exist in the pixel cache, the proposed architecture performs a prefetch operation in order to reduce the miss penalty of the pixel cache. That is, the cache miss penalty can be reduced as the transfer of a missed cache block from the frame memory into the pixel cache can be handled simultaneously with the rasterization pipeline executions. Simulation results show that the proposed architecture can achieve a performance gain of about 32 percent compared with the conventional pretexturing architecture and about 7 percent compared to the hierarchical z-buffer visibility scheme

This research is to design a high performance NAND-type flash memory package with a smart buffer cache that enhances the exploitation of spatial and temporal locality. The proposed buffer structure in a NAND flash memory package, called as a smart buffer cache, consists of three parts, i.e., a fully-associative victim buffer with a small page size, a fully-associative spatial buffer with a large page size, and a dynamic fetching unit. This new NAND-type flash memory package can achieve dramatically higher performance and lower power consumption compared with any conventional NAND-type flash memory module. Our results show that the NAND flash memory package with a smart buffer cache can reduce the miss ratio by around 70% and the average memory access time by around 67%, over the conventional NAND flash memory configuration. Also, the average miss ratio and the average memory access time of the package module with smart buffer cache for a given buffer space (e.g., 3 KB) can achieve better performance than package modules with a conventional direct-mapped buffer with eight times (e.g., 32 KB) or than a fully-associative configuration with twice as much space (e.g., 8 KB).

We present a selective filter-bank translation lookaside buffer (TLB) system with low power consumption for embedded processors. The proposed TLB is constructed as multiple banks, with a small two-bank buffer, called as a filter-bank buffer, located above its associated bank. Either a filter-bank buffer or a main bank TLB can be selectively accessed based on two bits in the filter-bank buffer. Power savings are achieved by reducing the number of entries accessed at a time, by using filtering and bank mechanism. The overhead of the proposed TLB turns out to be negligible compared with other hierarchical structures. That is, the two-cycle overhead of the proposed TLB is only about 3%, as compared with the 6% overhead of filter (micro)-TLB and the 9% overhead of banked-filter TLB. We show that the average hit ratios of the filter-bank buffers and the main banks of the proposed TLB are 88 and 12%, respectively. Therefore, significant power savings can be achieved with just a small performance degradation. The Power×Delay product can be reduced by about 88% compared with a fully associative TLB, 67% with respect to filter-TLB, and 37% relative to banked-filter TLB.

The authors design and implement a dynamic and effective communication MPI (Message-Passing Interface) library for the grid environment, especially to design collective operations such as broadcast and reduce. The purpose of the grid environment is to aggregate a large number of resources. So, it is inevitable that networks will be heterogeneous, and thus application performance will be affected. However, these issues have not until now been considered in designing communication primitives. Thus, these characteristics from the grid networks are specified and adapted into the communication algorithm design in this research. For an effective solution, we characterize the grid network on the basis of actual measurement, and design an effective communication algorithm called HLOT (Hierarchical Latency Optimal Tree) that can reduce the communication delay by utilizing the network status aggressively. Also, by using the proposed algorithm, we implement various collective communication routines of MPI li...

Decompression time is the largest overhead in online compression techniques, and may offset any benefit obtained by compression. This article presents the upper bounds of decompression overhead required to achieve performance improvement in compressed memory systems and proposes several effective techniques for reducing or hiding decompression overhead. These techniques include selective compression, the choice of X-RL algorithm, early restarting, overlapped decompression, and use of a decompression buffer. Moreover. the conceptual architecture of a compressed memory system using the proposed techniques is suggested. These techniques are evaluated via simulation. The simulation results show that the proposed techniques can sufficiently reduce the decompression overhead to attain performance improvement against conventional memory systems.

This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache equally effective for general-purpose as well as multimedia applications. Our cache organization and operational mechanism are especially designed to maximize temporal locality and spatial locality, selectively and adaptively. Simulation shows that the average memory access time of the proposed cache is equal to that of a conventional direct-mapped cache with eight times as much space. In addition, the simulations show that our cache achieves better performance than a 2-way or 4-way set associative cache with twice as much space. The average miss ratio, compared with the victim cache with 32-byte block size, is improved by about 41% or 60% for general applications and multimedia applications, respectively. It is also shown that power consumption of the proposed cache is around 10% to 60% lower than other cache systems that we examine. Our cache system thus offers high performance with low power consumption and low hardware cost.

We present a simple but high performance translation lookaside buffer (TLB) system with low power consumption for use in embedded systems. Our TLB structure supports two page sizes dynamically and selectively to achieve high performance with low hardware cost. To minimize power consumption, a banked-TLB is constructed by dividing one fully associative (FA) TLB space into two separate FA TLBs. These two structures are integrated to form a banked-promotion (BP) TLB. Promotion overcomes the unbalanced utilization of a banked-TLB by moving adjacent entries out of the primary banks into a separate super-page TLB. Simulation results show that the Energy* Delay product can be reduced by about 99.8%, 19.2%, 24.2%, and 24.4% compared with a FA TLB, a micro-TLB, a banked-TLB, and a victim-TLB respectively. Therefore, the BP TLB offers high performance with low power consumption and low hardware cost.

On-line data compression is a new alternative technique for improving memory system performance, which can increase both the effective memory space and the bandwidth of memory systems. However, decompression time accompanied by accessing compressed data may offset the benefits of compression. In this paper, a selectively compressed memory system (SCMS) based on a combination of selective compression and hiding of decompression overhead is proposed and analyzed. The architecture of an efficient compressed cache and its management policies are presented. Analytical modeling shows that the performance of SCMS is influenced by the compression efficiency, the percentage of references to the compressed data block, and the percentage of references found in the decompression buffer. The decompression buffer plays the most important role in improving the performance of the SCMS. If the decompression buffer can filter more than 70% of the references to the compressed blocks, the SCMS can significantly improve performance over conventional memory systems.

This research explores a compressed memory hierarchy model which can increase both the effective memory space and bandwidth of each level of memory hierarchy. It is well known that decompression time causes a critical effect to the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed memory systems. This paper proposes a selective compressed memory system (SCMS) incorporating the compressed cache architecture and its management method. To reduce or hide decompression overhead, this SCMS employs several effective techniques, including selective compression, parallel decompression and the use of a decompression buffer. In addition, fixed memory space allocation method is used to achieve efficient management of the compressed blocks. Trace-driven simulation shows that the SCMS approach can not only reduce the on-chip cache miss ratio and data traffic by about 35% and 53%, respectively, but also achieve a 20% reduction in average memory access time (AMAT) over conventional memory systems (CMS). Moreover, this approach can provide both lower memory traffic at a lower cost than CMS with some architectural enhancement. Most importantly, the SCMS is a more attractive approach for future computer systems because it offers high performance in cases of long DRAM latency and limited bus bandwidth.

The static specification of operations executed in parallel using No Operations (NOPs) is another culprit to make code size to be increased in VLIW architecture. Some alternatives in the instruction encoding and memory subsystem are proposed to minimize the impact of NOP on the code size. One is the compressed cache using the packed encoding scheme and the other is the decompressed cache using the unpacked encoding scheme. The compressed cache shows high memory utilization but increases the pipeline branch penalty because it requires very complex fetch hardware. On the contrary, the fetch overhead can be decreased in the decompressed cache because the unpacked encoding scheme allows an instruction to be issued to the pipeline without any recovery process. However, it has a shortcoming that the memory utilization is deteriorated due to the memory allocation irrespective of the number of useful operations. In this research, a new instruction encoding scheme called a semi-packed encoding scheme and the section cache, which enables effective store and retrieval of semi-packed instructions, are proposed. This can decrease the hardware complexity to fetch an instruction and the wasted memory space due to NOPs via the partially fixed length of an instruction. The experimental results reveal that the memory utilization in the section cache is 3.4 times higher than in the decompressed cache. The memory subsystem using the section cache can provide about 15% performance improvement with the moderate size of chip area.

A data cache system is designed as low power/high performance cache structure for embedded processors. Direct-mapped cache is a favorite choice for short cycle time, but suffers from high miss rate. Hence the proposed dual data cache is an approach to improve the miss ratio of direct-mapped cache without affecting this access time. The proposed cache system can exploit temporal and spatial locality effectively by maximizing the effective cache memory space for any given cache size. The proposed cache system consists of two caches, i.e., a direct-mapped cache with small block size and a fully associative spatial buffer with large block size. Temporal locality is utilized by caching candidate small blocks selectively into the direct-mapped cache. Also spatial locality can be utilized aggressively by fetching multiple neighboring small blocks whenever a cache miss occurs. According to the results of comparison and analysis, similar performance can be achieved by using four times smaller cache size comparing with the conventional direct-mapped cache.And it is shown that power consumption of the proposed cache can be reduced by around 4% comparing with the victim cache configuration.

The memory-based processor array (MPA) was previously designed as an effective memory-processor integrated architecture. The MPA can be easily attached into any host system via memory interface. In this paper, the impact of the memory interface structure is analytically analyzed for computer vision tasks. An analytical model is constructed to describe the characteristics of the memory interface structure. Performance improvement for the memory interface model of the MPA system can be 6–40% for vision tasks consisting of sequential and data parallel tasks. Mapping algorithms to implement convolution and connected component labeling on the MPA are also presented. The asymptotic time complexities of the algorithms are evaluated to verify the cost-effectiveness and the efficiency of the MPA system.

In the conventional floating point multipliers, the rounding stage is usually constructed by using a high speed adder for the increment operation, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it may accompany additional execution time and hardware components for renormalization which may occur by an overflow from the rounding operation. A floating-point multiplier performing addition and IEEE rounding in parallel is designed by optimizing the operational flow based on the characteristics of floating point multiplication operation. A hardware model for the floating point multiplier is proposed and its operational model is algebraically analyzed in this research. The floating point multiplier proposed does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

An approach for designing a hybrid parallel system that can perform different levels of parallelism adaptively is presented. An adaptive parallel computer vision system (APVIS) is proposed to attain this goal. The APVIS is constructed by integrating two different types of parallel architectures, i.e. a multiprocessor based system (MBS) and a memory based processor array (MPA), tightly into a single machine. One important feature in the APVIS is that the programming interface to execute data parallel code onto the MPA is the same as the usual subroutine calling mechanism. Thus the existence of the MPA is transparent to the programmers. This research is to design an underlying base architecture that can be optimally executed for a broad range of vision tasks. A performance model is provided to show the effectiveness of the APVIS. It turns out that the proposed APVIS can provide significant performance improvement and cost effectiveness for highly parallel applications having a mixed set of parallelisms. Also an example application composed of a series of vision algorithms, from low-level and medium-level processing steps, is mapped onto the MPA. Consequently, the APVIS with a few or tens of MPA modules can perform the chosen example application in real time when multiple images are incoming successively with a few seconds inter-arrival time.

Data-parallel implementations of the computationally intensive task of solving multiple quadratic forms (MQFs) have been examined. Coupled and uncoupled parallel methods are investigated, where coupling relates to the degree of interaction among the processors. Also, the impact of partitioning a large MQF problem into smaller non-interacting subtasks is studied. Trade-offs among the implementations for various data-size/machine-size ratios are categorized in terms of complex arithmetic operation counts, communication overhead, and memory storage requirements. Furthermore, the impact on performance of the mode of parallelism used is considered, specifically, SIMD versus MIMD versus SIMD/MIMD mixed-mode. From the complexity analyses, it is shown that none of the algorithms presented in this paper is best for all data-size/machine-size ratios. Thus, to achieve scalability (i.e., good performance as the number of processors available in a machine increases), instead of using a single algorithm, the approach discussed is to have a set of algorithms from which the most appropriate algorithm or combination of algorithms is selected based on the ratio calculated from the scaled machine size. The analytical results have been verified by experiments on the MasPar MP-1 (SIMD), nCUBE 2 (MIMD), and PASM (mixed-mode) prototype.

In Smartphone a touch screen has changed the paradigm of user interface on personal computing devices just through single software rather than hardware keyboards and number pads. Therefore it is receiving most of the attention as mobile UX (User eXperience). This paper explores the process of touch event and the feasibility of increasing the performance of it on Android Froyo and Gingerbread. For this purpose, this paper suggests a technique to improve the performance of touch event screen update by using virtual touch event without being synchronized to touch event. The simulation results show that the proposed method can increase 15% of performance on processing the number of frames as for frame per second.

This paper presents an enhanced virtual object management scheme for a personalized ubiquitous computing service, Virtual Personal World (VPW), at peer-to-peer. In the proposed scheme, more detailed descriptions for virtual objects are added in addition to the existing definitions on communications and data of them, and then two phases of virtual object discovery scheme are applied. Therefore, the management scheme can be individualized more effectively according to users' preferences and behaviors and provide a fast way of finding virtual objects. For performance verification, we have implemented a prototype of the proposed scheme as a part of VPW and compare the speed of finding virtual objects in the proposed scheme with those in other DHT P2P networks. Simulation results shows that the proposed scheme can achieve performance improvements compared with other P2P networks.

Mixed-mode parallel processing systems are capable of executing in either SIMD (synchronous) or MIMD (asynchronous) mode of parallelism. The ability to switch between the two modes at instruction-level granularity with very little overhead allows the parallelism mode to vary for each portion of an algorithm. To fully exploit the capability of intermixing both SIMD and MIMD operations within a single program, one must determine the optimum mapping of an algorithm to the mixed-mode architecture. The phase optimization technique, where the programmer makes an implicit assumption that by combining the best version of each phase the optimal implementation of the entire program will be achieved, generally works in a serial computer environment. The application of this approach to the selection of a mode of parallelism for each phase is investigated by presenting a detailed study of a practical image-processing application, the Edge-Guided Thresholding algorithm, and its mapping to a mixed-mode parallel architecture. The six functional phases of the algorithm, as well as their temporal juxtaposition, are analyzed along with experimental performance measurements obtained from the PASM parallel processing prototype, a mixed-mode system. The results discussed here demonstrate a situation in which the advantages of a mixed-mode approach are limited.

A model for overlapped operation between the control unit (CU) and processing elements (PEs) in an SIMD machine is presented. The major requirements and structure of the CU for overlapped operation in SIMD mode are described and overlapped operation is formally defined. To use the computing power of both the CU and the PEs most effectively to execute a single program, a balanced work load between the CU and PEs is required. It is assumed that certain computations (e.g., the manipulation of loop index variables, PE-common array index calculations) can be migrated from the PEs to the CU and vice versa.This research demonstrates how to increase the effectiveness of an SIMD machine by allowing overlapped operation between the CU and PEs. The best overlapping can be achieved ideally by assigning an equal amount of work to be executed concurrently on the CU and PEs, resulting in a 2N speedup for an N-PE system. The goal of this research is to develop a model of overlapped operation in SIMD mode so that the actual maximum possible performance of the SIMD machine can be attained.

Human activity recognition is an important task in providing contextual user information. In this study, we present a methodology to achieve human activity recognition using a Smartphone accelerometer independent of a subject compared with other user-dependent solutions. The proposed system is composed of four components; a data collector, a data storage cloud, a workstation module and an activity recogniser. The data collector extracts a unique set of defined features from raw data and sends them to the data storage cloud. The workstation module receives the training data from the cloud and generates classification models. The activity recogniser determines the user's current activity based on up-to-date available classifier from the cloud. A prototype is implemented on an android platform to recognise a set of basic daily living activities by placing the Smartphone in different positions to the user and evaluated for offline and online testing to show the scalability and effectiveness.

Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. There are many methods for improving TLB performance, such as increasing the number of entries in TLB and supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. Also software must select a proper page-size assignment policy to take advantage of the larger pages. So, we propose a new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to result of comparison and analysis, the proposed method with fewer entries results in similar performance compared with the conventional TLB with many entries. Also in the case of same area size, it is shown that miss ratio of the proposed TLB can be reduced by as much as 90% comparing with conventional fully-associative TLB.