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This review explains the historical perspective of single-event effects, single-event transitions, and single-event upsets. It delves into the concept of critical charge and offers a comprehensive classification of single-event upsets. The main aspects of this work involve an explanation of the root causes of soft errors in VLSI circuits. The primary source of radiation in the space environment is thoroughly analyzed, discussing particle generation and interactions. This examination includes the behavior of energetic alpha particles and their interactions in silicon, as well as the impact of high-energy neutrons and nuclear interactions in silicon. Additionally, the study presents a detailed exploration of soft error simulation and calculation methods, enabling the estimation of soft error rates (SERs) and mean time to failure (MTTF). The focus of this research is the investigation of soft errors in memory and sequential circuitry, demonstrating the potential risks posed by these errors in electronic systems. The findings of this research provide a valuable foundation for developing strategies to mitigate soft errors and enhance the reliability of VLSI circuits for space applications. To highlight understanding, we have ended most of the sections and subsections with the questions. These questions can help researchers explore related research directions. [ABSTRACT FROM AUTHOR]

Soft errors induced by radiation are the major reliability threat for SRAM-based field-programmable gate arrays (FPGAs). A more detailed analysis of the soft error sensitivity of the 40 nm SRAM-based FPGA was performed. Experimental methods for the configurable logic module, configure memory cells, and block RAM have been introduced for measuring the single event effects (SEEs) induced by alpha particles using a 241Am radiation source. The single event upset (SEU) and single event functional interrupt (SEFI) cross sections of different functional blocks have been calculated to discuss the failure mechanisms of the FPGA. The SEEs test results for the FPGA device based on the 40 nm CMOS process are significant. [ABSTRACT FROM AUTHOR]

Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell's stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell's reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions. [ABSTRACT FROM AUTHOR]