Search

Analysis of temporal masking effects of single-event upsets (SEUs) on master–slave flip-flops (FFs) is provided, considering the difference of SEU cross sections between master and slave latches. An improved model of temporal masking effects of SEUs in master–slave FFs is proposed and demonstrated through alpha-particle single-event effect (SEE) experiments. Based on the improved model, an effective and accurate methodology to quantitatively evaluate single-event transient and SEU-induced error cross sections of FF chains is proposed. Implications of SEE hardening for sequential circuits are discussed. [ABSTRACT FROM AUTHOR]

Reductions in single-event (SE) upset (SEU) rates for sequential circuits due to temporal masking effects are evaluated. The impacts of supply voltage, combinational-logic delay, flip-flop (FF) SEU performance, and particle linear energy transfer (LET) values are analyzed for SE cross sections of sequential circuits. Alpha particles and heavy ions with different LET values are used to characterize the circuits fabricated at the 40-nm bulk CMOS technology node. Experimental results show that increasing the delay of the logic circuit present between FFs and decreasing the supply voltage are two effective ways of reducing SE error rates for sequential circuits for particles with low LET values due to temporal masking. SEU-hardened FFs benefit less from temporal masking than conventional FFs. Circuit hardening implications for SEU-hardened and unhardened FFs are discussed. [ABSTRACT FROM PUBLISHER]

Synergetic effects of total-ionizing-dose irradiation on the single event upset (SEU) and single event transient (SET) performance of 40-nm sequential circuits are studied at doses up to 2 Mrad(SiO2). The impacts of input pattern and supply voltage are evaluated. An initial increase of SEU- and SET-induced soft error cross-section versus total dose is observed, followed by a decreasing trend at higher doses. The maximum increase of SEU- and SET-induced soft error cross-section occurs when the total-ionizing-dose is approximately 1.5 Mrad(SiO2) in the studied sequential circuit. The SET-induced soft error cross-section versus total dose increases at a faster speed than the SEU-induced soft error cross-section. [ABSTRACT FROM PUBLISHER]

Flip-flop soft errors caused due to direct strikes on flip-flops as well as soft errors caused due to latched transients from combinational logic show frequency dependence. This frequency dependence in the case of high-speed sequential circuits can derate the soft error rate by as much as 5X. Circuit variables, such as voltage, frequency, logic delay, as well as environmental factors, such as particle type and linear energy transfer that affect the frequency dependence are studied. Heavy-ion irradiation of 28-nm sequential circuits shows that the cross-section decreases with frequency for low-LET particles and increases with frequency for higher-LET particles. Competing trends involving combinational logic and flip-flops are shown to be the reason. The voltage dependence of this trend is evaluated. The key insight that emerges from this work is that at sufficiently high frequencies, the cross-section of certain sequential circuits can be lower than that at lower frequencies. Similarly, lowering voltage may not always result in increased soft error rate at certain frequencies. [ABSTRACT FROM PUBLISHER]

Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes. [ABSTRACT FROM PUBLISHER]

Alpha particle irradiations of 28-nm combinational logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the combinational logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from combinational logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies. [ABSTRACT FROM PUBLISHER]

It has been predicted that upsets due to Single-Event Transients (SETs) in logic circuits will increase significantly with higher operating frequency and technology scaling. For synchronous circuits manufactured at advanced technology nodes, errors due to single-event transients are expected to exceed those due to latch upsets. Experimental results presented in this paper quantify the contribution of logic errors to the total Soft-Error Rate (SER) for test circuits fabricated in a 40 nm bulk CMOS technology. These results can be used to develop guidelines to assist circuit designers adopt effective hardening strategies to reduce the SER, while meeting performance specifications for high speed logic circuits. [ABSTRACT FROM PUBLISHER]