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We reported on statistical behavioral models of silicon ring resonators at a commercial CMOS foundry. The ring resonators were fabricated on 300 mm silicon-on-insulator wafers using the DAPHNE technology at STMicroelectronics. Process variability, including lot-to-lot, wafer-to-wafer, and field-to-field variation, is inferred from optical test results, and cross validated by inline metrology data. Significant amount of reflection is observed in many ring designs, and the impacts of reflection on system integration are discussed. [ABSTRACT FROM AUTHOR]

Wideband polarization beam splitters (PBS) are a key building block in polarization management circuits for wavelength division multiplexing applications. A broadband PBS on a 300-mm silicon nitride (SiN) photonic platform is reported based on phase-controlled directional coupler (DC). Unlike classical DC-based PBS made on silicon, the proposed configuration leverages the comparatively lower birefringence in SiN to yield wideband and efficient splitting. A semi-analytical approach, based on transfer matrix modeling and 3-D finite difference time domain, has been used to design and optimize the structure for O-band operation. The proposed PBS has been experimentally demonstrated showing insertion loss (IL) lower than 0.6 dB and extinction ratio (ER) as high as 10 dB over 95-nm bandwidth for both polarizations. Furthermore, this simplified architecture eases cascading, allowing the demonstration of IL below 1.1 dB and ER larger than 24 dB over 85-nm wavelength range in a dual-stage configuration. [ABSTRACT FROM AUTHOR]

Keeping up with bandwidth requirements in next generation short- and long-reach optical communication systems will require migrating from simple modulation formats such as on-off keying to more advanced formats such as quaternary phase-shift keying (QPSK). In this paper, we report the first demonstration of QPSK signal generation in the O-band using a silicon dual-drive Mach–Zehnder modulator (DD-MZM). The performance of the silicon DD-MZM is assessed at 20 Gb/s and compared against a similar DD-MZM based on LiNbO3, showing a limited implementation power penalty of only 1.5 dB. [ABSTRACT FROM AUTHOR]

Industrial implementation of a silicon photonics platform using 300-mm SOI wafers and aiming at 100 Gb/s aggregate data-rate application is demonstrated. The integration strategy of electronic and photonic ICs, 300-mm process flow, and process variability are discussed, and performances of the passive and active optical devices are shown. An example of a low-cost LGA-based package together with a fiber assembly is given. RX and TX circuits operating at 25 Gb/s are demonstrated. Finally, the process evolution toward the integration of the backside reflector and multiple silicon etching level is demonstrated. [ABSTRACT FROM PUBLISHER]

This paper presents a 50 Gb/s per lane hybrid BiCMOS and silicon photonic integrated circuit for use in fiber optic communications. Fine pitch copper pillars are used to integrate electronics and silicon photonics. The resulting device demonstrates the generation and detection of up to 56 Gb/s NRZ optical signals over 2-km standard single-mode fiber at 1310-nm wavelength. At 40 Gb/s, the link operates error free, and at 56 Gb/s well below KR4 RS-FEC operating BER. The power dissipation of TX including CW laser is 600 mW (450-mW driver, 150-mW CW laser), RX is 150 mW, resulting in total per channel of less than 750 mW. [ABSTRACT FROM PUBLISHER]