Search

Abstract: We present the fabrication and characterization of ultra thin and relatively thick SiGe-On-Insulator wafers with different Ge contents prepared by Ge condensation technique. The fabrication procedures as well as the structural analysis are detailed. The electrical properties of advanced strained SiGe-On-Insulator (SGOI) and relaxed Germanium-On-Insulator (GeOI) wafers were investigated using the Pseudo-MOSFET method and then compared with Silicon-On-Insulator (SOI) and strained Silicon-On-Insulator (sSOI) structures. GeOI wafers with 10-nm and 100-nm film thickness show exceptionally high hole mobility as compared to both SOI and sSOI structures. The hole mobility can reach 400cm2/Vs. It is found that the mobilities for holes and electrons vary in opposite directions as the Ge fraction is increased. The Ge content also impacts the threshold and flat-band voltages. [Copyright &y& Elsevier]

Abstract: The abundance of work on SiGe based devices demonstrates the importance of compositional characterization of such materials. However, SIMS characterization of SiGe layers often suffers from matrix effects due to non-linear variation of ionization yields with Ge content. Moreover, the presence of oxide in these layers would definitely increase the difficulty to obtain quantitative profiles by SIMS. We highlight here the improvements brought by the extended Full Spectrum protocol, presented in previous works and allowing minimization of matrix effects in SiGe matrices compared with more classic protocols. This results in more accurate depth profiles, and thus brings better comprehension of the behavior of intrinsic and doped layers under dry or wet oxidizing. [Copyright &y& Elsevier]

Abstract: In a 300mm industrial Reduced Pressure–Chemical Vapour Deposition tool we have assessed the advantages and drawbacks of disilane for the low temperature growth of Si and SiGe. Four distinct regions can be noticed on the Arrhenius plot of the Si growth rate at 2660Pa (i.e. 20Torr) from Si2H6 as a function of the reverse growth temperature. For T>850°C, we are in the high temperature, Si precursor supply-limited regime (as with SiH4). For T≤850°C, the situation is more complicated, with the presence of a growth rate “plateau” between 575°C and 675°C (not present for SiH4 or SiH2Cl2), surrounded by domains where the Si growth rate increases with the temperature at different rates (Ea =1.39eV (T>675°C)⇔Ea =2.30eV (T<575°C)). This translates into Si growth rates which, for T<575°C, are approximately ten times higher with Si2H6 than with SiH4, which are in turn roughly ten times higher than with SiH2Cl2. For given GeH4 and Si precursor mass–flow ratios, lower Ge contents and much higher SiGe growth rates are obtained at 550°C, 2660Pa with Si2H6 than with SiH4 and especially SiH2Cl2. SiGe and Si layers grown with disilane are generally of high crystalline quality, however moderate Si2H6 mass-flows should be used in the growth rate plateau, in order to avoid the formation of defective Si. [Copyright &y& Elsevier]

Abstract: The abundance of work on SiGe based devices demonstrates the importance of compositional characterization of such materials. However accurate SIMS depth profiling of SiGe, and especially of SiGe/silicon dioxide interfaces can be difficult due to matrix effects. Therefore, we highlight here the improvements brought by the extended Full Spectrum protocol, presented in previous works and allowing minimization of matrix effects. Previous studies on this protocol showed that it was extremely precise and reproducible for Ge and impurity quantification in non oxidized matrices. In this study we thus investigated its accuracy for simultaneous quantitative depth profiling of both matrix elements (Si, Ge, O) and impurities (C) in Si0.82Ge0.16C0.02 layers annealed in oxidizing atmosphere, by comparing results with more classic protocols. The profiles provided by the extended Full Spectrum protocol were found to be more accurate than the others, especially around interfaces. This results in a better comprehension of the behaviour of SiGeC layers under oxidizing anneal and thus allows the fabrication of very well controlled three dimensional Ge nanowire structures for next generation devices. [Copyright &y& Elsevier]