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We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of $1.8 \mu \text{m}$ and active area of 0.104 mm2 achieves a breakdown voltage of 1086 V and a specific ON-resistance of 0.98 $\text{m}\Omega \,\cdot $ cm2. The first-quadrant output and transfer characteristics are presented, from which the ON-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the ${x}$ -direction and trapezoidal mesas in the ${y}$ -direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ($\vert {V}_{\text{on}}\vert $) and the maximum current before gate junction turn-on (${J}_{\text{umax}}$). The third-quadrant performance can be improved by using forward-on gate voltage, a $\vert {V}_{\text{on}}\vert $ lower than 0.2 V (at 100 A/cm2) and a ${J}_{\text{umax}}$ larger than 500 A/cm2 are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications. [ABSTRACT FROM AUTHOR]

This article presents the design and fabrication results of the silicon carbide (SiC) super-junction Schottky barrier diode (SBD). The impact of two key device structure parameters, i.e., mesa width (MW) and trench width (TW), on the device forward and reverse performance is studied by numeric simulations and measurements. Furthermore, a simple and efficient termination structure, i.e., wide-trench termination, is proposed to protect the device edge. With this termination, the simulated device breakdown voltage is significantly increased from 1423 to 2600 V with a wide-trench termination width (WTW) larger than $20~\mu \text{m}$. The outermost MW (OMW) of the transition region is also investigated. It is found that the narrower OMW can mitigate the electric field crowding at the top of the outermost mesa and reduce the electrical stress of the dielectric. Devices with different structural parameters are fabricated and measured. The device with WTW $= 50\,\,\mu \text{m}$ and the optimum OMW demonstrates the highest breakdown voltage of 1920 V. The specific ON-resistance (${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$) of this device is 1.6 $\text{m}\Omega \cdot $ cm2. Subtracting the substrate resistance, the ${R}_{{\rm \scriptscriptstyle {ON}},\text {sp}}$ is only 1.2 $\text{m}\Omega \cdot $ cm2. Such device performance successfully breaks the theoretical 1-D limit of the SiC unipolar device. Furthermore, the leakage current path of the fabricated device is investigated by thermal emission microscope (EMMI). Future improvements to reduce the leakage current are also provided. [ABSTRACT FROM AUTHOR]

For the termination in high-voltage SiC thyristor, this article proposes a single-mask implantation-free solution named aperture density modulation technique. Using this technique, the etching profile on the epitaxial layer can be controlled by the aperture layout on the mask. Thus, it can directly form the smoothly tapered junction termination extension with customizable slope profile. The experiments confirm this control ability on profiles with the extension length from 200 to 400 μm. The fabricated devices with the blocking voltage near 8 kV (~80%) demonstrate the feasibility as a termination technique. The numerical simulations present the potential to maintain this breakdown voltage within 120 μm. Therefore, a low-cost solution for high-voltage termination in SiC bipolar devices is expected using this technique. [ABSTRACT FROM AUTHOR]

Termination design for 4H-SiC super-junction devices based on “trench-etching and implantation” technology, has been discussed through 3D numeric simulations and experiments. It is found that the existing design concept of super-junction termination extension (SJTE) structure is no longer capable of blocking high voltage due to the hole accumulation on the trench sidewall. In order to provide sufficient protection for the device edge, a novel device structure, i.e., hybrid termination of wide trench and SJTE (WT-SJTE), is proposed. With such WT-SJTE structure, the simulated device breakdown voltage can be improved from 700V to 800V. Furthermore, through the narrow termination mesa design, as predicted by numeric simulations, a noticeable improvement were measured, and a breakdown voltage of 960V was experimentally demonstrated. These results show the effectiveness of the WT-SJTE with such narrow termination mesa design. [ABSTRACT FROM AUTHOR]

Conventional power semiconductor devices suffer from a well-known performance limit. Floating Island (FI) structure can break the limit by inserting multiple oppositely doped islands into the drift layer and is suitable for silicon carbide (SiC) devices. In this article, the FI devices are classified into two distinct types according to the doping level of the islands, which are referred to as field-stop FI (FSFI) with highly doped island and fully depleted FI (FDFI) with medium-doped island. The theoretical limits for both types are revealed through 1-D modeling. The FDFI is found to be endowed with 12% lower specific ON-resistance than FSFI. To facilitate the comprehensive design of FDFI devices, 2-D analytical models for both conducting state and blocking state are established and verified by numeric simulation. By virtue of the 2-D models, charge balance effect of FDFI is illuminated, and parametric optimization for 2-, 4-, and 6-kV rated devices is performed. The optimal designs are presented and also simulated numerically. The results from models and numeric simulations show good agreement. The analytical models in this article are proved to be rather effective and can be helpful in revealing the mechanism of FI devices as well as in optimizing FI devices. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) super-junction JFET was designed, simulated and fabricated through trench-etching and sidewall-implantation technology, which avoids the expensive epi-regrowth process. The fabricated super-junction JFET achieves a breakdown voltage of 1000V with specific on-resistance of 1.3m $\Omega ~\cdot \text {cm}^{{2}}$. The threshold voltage (${V}_{\text {th}}$) is stable over a wide range of temperature with less than 0.2V shift from 25°C to 175°C. These results demonstrate that the trench-etching and sidewall-implantation technology is a promising option to fabricate SiC super-junction devices. These devices could have great potential for future power electronics. [ABSTRACT FROM AUTHOR]

Trench termination with SiO2-encapsulated dielectric for 4H-SiC devices is proposed and experimentally demonstrated. The trench is mainly refilled with spin-on dielectric which is encapsulated with SiO2to protect it from the high electric field in the trench. Such a trench termination is fabricated along with a high-voltage p-i-n diode. The fabricated device shows a repeatable breakdown voltage over 1750 V (96% of the ideal planar junction breakdown) with a termination length of $14~\mu \text{m}$ while the conventional trench termination has unrepeatable breakdown and requires over $30~\mu \text{m}$ termination length. Also, this termination length is less than ~ 1/4 of the dimension of a field limiting rings termination. Moreover, the fabrication process is robust with a large process window (Trench width ≥ 14 $\mu \text{m}$). [ABSTRACT FROM AUTHOR]

In the above letter , the epi doping listed in was wrong, and it should be $8\times 10^{15}$ cm−3 which is the same the value as mentioned in the main text. The corrected table is listed below. [ABSTRACT FROM AUTHOR]