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In this work, border traps located in SiO2 at different depths in 4H-SiC MOS system are evaluated by a simple and effective method based on capacitance-voltage (C-V) measurements. This method estimates the border traps between two adjacent depths through C-V measurement at various frequencies at room and elevated temperatures. By comparison of these two C-V characteristics, the correlation between time constant of border traps and temperatures is obtained. Then the border trap density is determined by integration of capacitance difference against gate voltage at the regions where border traps dominate. The results reveal that border trap concentration a few nanometers away from the interface increases exponentially towards the interface, which is in good agreement with previous work. It has been proved that high temperature 1 MHz C-V method is effective for border trap evaluation. [ABSTRACT FROM AUTHOR]

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17 μm in thickness with 5 × 1015 cm−3 n-type doping, and the channel length is 1 μm. The MOSFETs show a peak mobility of 17 cm2/V·s and a typical threshold voltage of 3 V. The active area of 0.028 cm2 delivers a forward drain current of 7 A at VGS = 22 V and VDS = 15 V. The specific on-resistance (Ron,sp) is 18 mΩ·cm2 at VGS = 22 V and the blocking voltage is 1975 V (IDS < 100 nA) at VGS = 0 V. [ABSTRACT FROM AUTHOR]

Charge trapping behavior and its origin in Al2O3/SiC MOS structure are investigated by analyzing the capacitance–voltage (C–V) hysteresis and the chemical composition of the interface. The C–V hysteresis is measured as a function of oxide thickness series for an Al2O3/SiC MIS capacitor. The distribution of the trapped charges, extracted from the C–V curves, is found to mainly follow a sheet charge model rather than a bulk charge model. Therefore, the electron injection phenomenon is evaluated by using linear fitting. It is found that most of the trapped charges are not distributed exactly at the interface but are located in the bulk of the Al2O3 layers, especially close to the border. Furthermore, there is no detectable oxide interface layer in the x-ray photoelectron spectroscope (XPS) and transmission electron microscope (TEM) measurements. In addition, Rutherford back scattering (RBS) analysis shows that the width of the Al2O3/SiC interface is less than 1 nm. It could be concluded that the charge trapping sites in Al2O3/SiC structure might mainly originate from the border traps in Al2O3 film rather than the interface traps in the interfacial transition layer. [ABSTRACT FROM AUTHOR]