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The authors investigate the effect of laser-induced heating on Raman measurements for different unpatterned and patterned substrates, including pure silicon, strained-silicon-on-insulator, and silicon-germanium layers on silicon. The relationship between heating and incident power of the laser used for Raman measurements is derived for unpatterned substrates, and the much stronger heating effects for line and island structures are shown. Additionally, the enormous heating of isolated silicon particles within the laser beam was investigated. The measured shifts clearly show that heating has to be considered even for moderate laser intensity when accurate stress measurements on such substrates are performed by Raman spectroscopy. [ABSTRACT FROM AUTHOR]

In this paper, intensity enhancements of the Raman signal from strained silicon films utilizing the tip enhanced Raman spectroscopy (TERS) effect are reported. Specially shaped metallized atomic force microscopy tips have been prepared by sputter deposition of thin silver films onto sharpened quartz tips and subsequent focused ion beam (FIB) modification. Raman signal enhancements of more than 20%, which are attributed to the strained silicon film of 70 nm thickness only, have been obtained due to approaching the TERS tips the laser spot. On samples with patterned trench structures prepared by FIB milling, lateral sample scans have been performed. These scans revealed a resolution of strained silicon lines with center-to-center distances below 250 nm, well below the classical optical diffraction limit. Based on an analysis of the stress state in the strained silicon structures, relaxation effects close to the trench edges have been investigated. The described approach of nano-Raman spectroscopy is promising for strain characterization in devices, e.g., in field-effect transistor structures. [ABSTRACT FROM AUTHOR]

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal-oxide-semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements. [ABSTRACT FROM AUTHOR]

Relaxation of stress generated inside through-silicon via (TSV), in regions of interconnect and regions of silicon adjusted to TSV by microstructure evolution during high-temperature anneal and by wafer/die cooling down to test/operation conditions, is critical for establishing a final equilibrium state. A model for stress relaxation governed by vacancy generation and migration is developed. The comparative study of the steady-state distributions of stress and concentrations of vacancies and plated atoms in via-last and via-middle TSVs allows us to conclude that different types of TSVs are characterized by miniscule differences in the level of generated stress. It is found that the grain size distribution along the TSV height can affect the level of generated stress. TSVs with the largest grains, located in the TSV center, and the smaller ones, located in the TSV top and bottom, seem to generate a smaller outside stress compared to other simulated grain size distributions. It is shown that additional stress gradients in interconnect segments, generated by nearby TSVs, can be relaxed at the proper planed anneal step. The performed simulation analysis allows us to conclude that the introduction of TSVs as a new element in 3-D IC stacking technology does not introduce any significant changes in the EM-related reliability. [ABSTRACT FROM PUBLISHER]

It is shown that Raman intensities of bulk and film in silicon-on-insulator substrates strongly depend on the incident angle of the exciting laser. In a backscattering geometry with perpendicular laser incidence, deflection at particles or atomic force microscopy tips can thereby lead to a selective enhancement of the film signal, which can be misinterpreted as surface/tip enhanced Raman scattering. The authors report strong enhancement effects by scattering at dielectric particles on silicon-on-insulator and silicon substrates as well as smaller effects for deflection at tips. In evaluating field enhancements on such substrates, this must be considered. [ABSTRACT FROM AUTHOR]

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far. [ABSTRACT FROM AUTHOR]

Abstract: Nanolithography based on local anodic oxidation (LAO) by atomic force microscopy is a promising technique for patterning strained film nanostructures on the silicon substrates. Due to its versatility and precise control, LAO is suited for preparing well defined calibration structures for local strain measurements. We investigated silicon–germanium patterns prepared by LAO and subsequent selective anisotropic wet etching. By combining the nanolithography and etching, dedicated strain test structures with a line width of 65nm were achieved and utilized for calibration of tip-enhanced Raman measurements. [Copyright &y& Elsevier]

Abstract: We investigated the effect of post annealing on the electrical and physical properties of atomic-layer-deposited thin HfO2, HfSi x O y and HfO y N z gate oxide films on Si. It was found that the main leakage conduction of all Hf-based oxide films was of the Poole–Frenkel (P–F) type in low electric fields and Fowler–Nordheim (F–N) conduction in higher fields. Also, it was observed that the transition from P–F to F–N of the annealed HfO y N z sample occurred earlier than that of the as-grown one. By using spectroscopic ellipsometry, it was found that the annealing process decreased the band gap of HfO2, HfSi x O y and HfO y N z films. From depth profile measurements on the HfO y N z film, we conclude that N moves toward the surface and interface during annealing. [Copyright &y& Elsevier]