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This paper presents a behavioral model for a Si/Si1−xGex multi-quantum well (MQW) detector that predicts device characteristics to investigate the effect of increasing Ge content in Si/Si1−xGex MQW. The modeling approach in this paper is based on a physical instead of empirical approach, which allows to obtain a predictive behavioral analysis of high Ge content with only a few fitting parameters. The model is used to simulate device transfer characteristics with respect to various amounts of Ge content used for Si1−xGex layer in MQW. The simulation results of the proposed model are validated with the experimental data. The simulated and the experimental data are consistent over a wide range of Ge content varied from 30% up to 50%. The primary objective of this paper is to optimize Ge content in the Si/Si1−xGex MQW detector to achieve desired thermal sensitivity measured in terms of temperature coefficient of resistance for a potential microbolometer application. This is the first study in the literature to develop such a highly predictive behavioral model of a Ge-enriched Si/Si1−xGex MQW. The study also presents the effect of including the carbon delta layers at the Si/Si1−xGex heterointerface on the device transfer characteristics. The effect of Ge content on the overall noise is also investigated by the noise characterization of the test devices. [ABSTRACT FROM AUTHOR]

This paper presents a predictive device model implemented by a self-consistent solution of Poisson–Schrödinger drift-diffusion formulation for a thermally sensitive detector based on a ${\mathrm {Si/Si}}_{{1}-{x}}{\mathrm {Ge}}_{{x}}$ multiquantum-well structure. The physical phenomena governing the carrier transport were modeled to investigate the effect of physical design aspects (Ge content, well periodicity, and well thickness). In particular, we have analyzed the effect of these physical design parameters on the carrier dynamics quantified by the dc performance in terms of net current density. A fully integrated simulation framework was developed and employed to optimize Ge content and device doping for a desired figure of merits specified by temperature coefficient of resistance (TCR) and dc resistance (${R}$). This methodology was successfully utilized to realize device profiles for various amounts of Ge content and optimization of (${R}$) geared for both high TCR and low noise. The dc performance metrics of the optimized profiles obtained by modeling presented here are compared and validated with the fabricated test devices. [ABSTRACT FROM AUTHOR]

Modern nanotechnology offers new possibilities to create artificial materials such as three-dimensional (3D) ordered island crystals that might be of interest e.g., for optoelectronic applications. We demonstrate that a completely self-organized body-centered tetragonal lattice of SiGe dots can be achieved by reduced pressure chemical vapor deposition (RPCVD). Main subject of this paper is the application of different X-ray diffraction techniques to study the structural properties of a large ensemble of buried SiGe dots with the target to optimize deposition conditions. This includes specular ω-2Θ scans to reveal vertical periodicity and strain state, reciprocal space mapping to determine lateral arrangement and symmetry of dots, and in-plane diffraction to get better inside to the lateral strain distribution close to the surface for further growth simulations. SEM cross-section images of a SiGe/Si superlattice of imperfect lateral periodic structure of SiGe dots. [ABSTRACT FROM AUTHOR]

C and Si delta doping in Ge are investigated using a reduced pressure chemical vapor deposition system to establish atomic-order controlled processes. CH 3 SiH 3 is exposed at 250 °C to 500 °C to a Ge on Si (100) substrate using H 2 or N 2 carrier gas followed by a Ge cap layer deposition. At 350 °C, C and Si are uniformly adsorbed on the Ge surface and the incorporated C and Si form steep delta profiles below detection limit of SIMS measurement. By using N 2 as carrier gas, the incorporated C and Si doses in Ge are saturated at one mono-layer below 350 °C. At this temperature range, the incorporated C and Si doses are nearly the same, indicating CH 3 SiH 3 is adsorbed on the Ge surface without decomposing the C Si bond. On the other hand, by using H 2 as carrier gas, lower incorporated C is observed in comparison to Si. CH 3 SiH 3 injected with H 2 carrier gas is adsorbed on Ge without decomposing the C Si bond and the adsorbed C is reduced by dissociation of the C Si bond during temperature ramp up to 550 °C. The adsorbed C is maintained on the Ge surface in N 2 at 550 °C. [ABSTRACT FROM AUTHOR]

Atomic layer doping of arsenic (As-ALD) in Si is investigated using a single wafer reduced pressure chemical vapor deposition tool. Hydrogen-free and hydrogen-terminated Si surfaces are exposed to AsH 3 in the temperature range between 300 °C and 700 °C followed by Si capping using H 2 –SiH 4 or H 2 –Si 2 H 6 gas mixture at 450–700 °C. After exposing to AsH 3 below 400 °C, no As spike formation is observed on both hydrogen-free and hydrogen-terminated Si surface. The incorporated As dose is increasing with increasing AsH 3 exposure time and saturates. Before saturation, a higher As dose is observed at higher AsH 3 partial pressure for the same AsH 3 exposure time. As incorporation is not influenced by the precursor (SiH 4 or Si 2 H 6 ) used for Si buffer deposition. By increasing SiH 4 or Si 2 H 6 partial pressure, a higher amount of As is incorporated at AsH 3 exposed surface and a higher background doping of segregated As in the Si cap is observed. The slope of the segregated As is not influenced by the growth rate at 600 °C, which means that the As segregation seems to be under thermal equilibrium. Lower segregation of As in the Si cap is observed at lower Si cap growth temperature. The results shown here may offer a precise location and dose control of As into Si. [ABSTRACT FROM AUTHOR]

Abstract: On the way to integrate lattice mismatched semiconductors on Si(001) we studied the Ge/Si heterosystem with the aim of a misfit dislocation free deposition that offers the vision to integrate defect-free alternative semiconductor structures on Si. Periodic Ge nano-structures (dots and lines) were selectively grown by chemical vapor deposition on Si nano-islands on silicon on insulator substrate with a thin (about 10nm) SiGe buffer layer between Si and Ge. The strain state of the structures was measured by grazing incidence and specular diffraction using laboratory-based X-ray diffraction technique. The SiGe improves the compliance of the Si compared to direct Ge deposition, prevents plastic relaxation during growth, and allows elastic relaxation before Ge is deposited on top. As a result, an epitaxial growth of Ge on Si fully free of misfit dislocations was achieved. [Copyright &y& Elsevier]

Abstract: The solid phase epitaxy (SPE) of undoped amorphous Si (a-Si) deposited on SiO2 patterned Si(001) wafers by reduced pressure chemical vapor deposition (RPCVD) using a H2–Si2H6 gas system was investigated. The SPE was performed by applying in-situ postannealing directly after deposition process. By transmission electron microscopy (TEM) and scanning electron microscopy, we studied the lateral SPE (L-SPE) length on sidewall and mask for various postannealing times, temperatures and a-Si thicknesses. We observed an increase in L-SPE growth for longer postannealing times, temperatures and larger Si thicknesses on mask. TEM defect studies revealed that by SPE crystallized epi-Si exhibits a higher defect density on the mask than at the inside of the mask window. By introducing SiO2-cap on the sample with 180nm Si thickness following postannealing at 570°C for 5 h, the crystallization of up to 450nm epi-Si from a-Si is achieved. We demonstrated the possibility to use this technique for SiGe:C heterojunction bipolar transistor (HBT) base layer stack to crystallize Si-buffer layer to widen the monocrystalline region around the bipolar window and to improve base link resistivity of the HBT. [Copyright &y& Elsevier]

Abstract: The selective epitaxial growth of germanium on nano-structured periodic silicon pillars and bars with 360nm periodicity on Si(001) substrate is studied to evaluate the applicability of nano-heteroepitaxy on the Ge–Si system for different fields of application. It is found that SiO2 used as masking material plays the key role to influence the strain situation in the Si nano-islands. To analyze this in detail, X-ray diffraction techniques in combination with theoretical simulations based on the kinematical X-ray scattering from laterally strained nano-structures and finite element method (FEM) calculations of the strain field are applied. The oxide related strain in the Si scales about linearly with the thickness of the SiO2 mask, but FEM simulations supposing a homogeneous stress distribution in the oxide are not sufficient to describe the local strain distribution in the nano-structures. It is demonstrated that the Ge lattice relaxes completely during growth on the Si nano-islands by generation of misfit dislocations at the interface, but a high structural quality of Ge can be achieved by suited growth conditions. [Copyright &y& Elsevier]

Abstract: Blanket and selective Ge growth on Si is investigated using reduced pressure chemical vapor deposition. To reduce the threading dislocation density (TDD) at low thickness, Ge deposition with cyclic annealing followed by HCl etching is performed. In the case of blanket Ge deposition, a TDD of 1.3×106 cm−2 is obtained, when the Ge layer is etched back from 4.5μm thickness to 1.8μm. The TDD is not increased relative to the situation before etching. The root mean square of roughness of the 1.8μm thick Ge is about 0.46nm, which is of the same level as before HCl etching. Further etching shows increased surface roughness caused by non-uniform strain distribution near the interface due to misfit dislocations and threading dislocations. The TDD also becomes higher because the etchfront of Ge reaches areas with high dislocation density near the interface. In the case of selective Ge growth, a slightly lower TDD is observed in smaller windows caused by a weak pattern size dependence on Ge thickness. A significant decrease of TDD of selectively grown Ge is also observed by increasing the Ge thickness. An about 10 times lower TDD at the same Ge thickness is demonstrated by applying a combination of deposition and etching processes during selective Ge growth. [Copyright &y& Elsevier]

Abstract: Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (100) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300°C at first to form two-dimensional Ge surface followed by thick Ge growth at 550°C. Root mean square of roughness (RMS) of ∼0.45nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4×108 cm−2 for a 4.7μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800°C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7×105 cm−2 is achieved for 4.7μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated. [Copyright &y& Elsevier]

We applied atomic layer processing for base doping of high performance SiGe:C heterojunction bipolar transistors (HBTs) fabricated within a 0.25 μm BiCMOS technology. B atomic layer doping (ALD) was performed at 400 °C during an interruption of the epitaxial SiGe:C base layer deposition. Atomic level dopant location and dose control was achieved.Electrical properties of atomic layer and box-profile doped (standard) HBTs were compared, showing peak fT and fmax for the ALD HBT of 113 and 127 GHz, and of 108 and 123 GHz for the standard HBT, respectively. The internal base sheet resistances (RSBi) for the ALD and standard HBTs were comparable, indicating very similar active B dose for both doping variants. The HBT results demonstrate the capability of atomic layer processing for doping of advanced devices, with critical requirements for dose and location control. [Copyright &y& Elsevier]

We show that AES depth profiling extended by a simple profile simulation technique allows characterization of details in the Ge concentration gradients for SiGe hetero-bipolar transistors (HBTs). Using the mixing-roughness-information depth (MRI) model to simulate the experimental data allows us to reveal concentration steps with a precision of about ±2 at.% and small deviations from linear concentration gradients. The obtainable high lateral resolution of AES facilitates an application for process optimization and control in small microelectronic structures. [Copyright &y& Elsevier]

Abstract: Among the many anticipated applications of graphene, some – such as transistors for Si microelectronics – would greatly benefit from the possibility to deposit graphene directly on a semiconductor grown on a Si wafer. We report that Ge(001) layers on Si(001) wafers can be uniformly covered with graphene at temperatures between 800°C and the melting temperature of Ge. The graphene is closed, with sheet resistivity strongly decreasing with growth temperature, weakly decreasing with the amount of deposited C, and reaching down to 2k . Density functional theory calculations indicate that the major physical processes affecting the growth are (1) substitution of surface Ge by C, (2) interaction between C clusters and Ge monomers, and (3) formation of bonds between graphene edge and Ge(001), and that the processes 1 and 2 are surpassed by CH2 surface diffusion when carbon is delivered from CH4. The results of this study indicate that graphene can be produced directly at the active region of the transistor in a process compatible with the Si technology. [Copyright &y& Elsevier]