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The ferroelectric (FE)-HfO2-based field-effect transistor (FEFET) is a promising candidate for emerging memory. However, data retention (DR) loss has been flagged as a key issue. Although two models of DR loss in FEFET have been proposed—the charge trapping model and the depolarization model—it is difficult to separate the dominant cause. In this article, simultaneous ${P}$ – ${V}$ and ${I}$ – ${V}$ measurements are performed which enable separation of these mechanisms. Different behavior of polarization and threshold voltage loss and recovery in a “set” state between two types of FEFET structures, metal (TiN)/FE-HfO2/SiO2/Si substrate (MFIS) and metal (TiN)/Si/FE-HfO2/SiO2/Si-substrate (MSFIS), clarify that the dominant mechanism of the DR loss in both structures is different. In addition, the impact of external bias and interfacial layer (IL) on the DR loss is revealed: the polarization loss is strongly affected by the external bias in both types of FEFET, indicating effective work function (eWF) has a strong impact on depolarization. On the other hand, the thickness and processing of IL strongly impact the charge trapping characteristics. Based on our understanding, excellent improvement of the DR is achieved: memory window ~0.8 V at 85 °C, extrapolated to ten years. [ABSTRACT FROM AUTHOR]

Abstract: For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon-hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices. [ABSTRACT FROM AUTHOR]

In this paper we investigate how geometry impacts the memory characteristics of 1-transistor dynamic floating body RAMs (FBRAMs) under total ionizing dose exposure. FBRAMs are implemented using fully depleted silicon-on-insulator devices with ultrathin buried oxide and body. Analytical models and experimental data are used to quantify the effects of charge trapping in the oxides and spacers on the memory read window shifts. The effects of increased radiation-induced leakage and interface trapping on the retention time are also discussed. Small geometry devices show reduced memory window shifts compared to large devices, but the retention time degradation is higher. The effects of coupling between interfaces and back-gate bias are also discussed in the context of memory characteristics. [ABSTRACT FROM AUTHOR]