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3-D stacks of complimentary metal–oxide–semiconductor (CMOS) integrated circuit (IC) chips for security applications monolithically embed backside buried metal (BBM) routing with low series impedance and high decoupling capability in a power delivery network (PDN), thanks to distributed capacitances over a full-chip backside area. The 3-D Si demonstrator integrating cryptographic engines was fabricated in a 0.13-μm CMOS technology with post-Si wafer-level BBM Cu processing with 10, 15, and 10 μm of thickness, linewidth, and space, respectively, along with through Si vias (TSVs) with 10 and 40 μm of diameter and depth, respectively. The capacitance of 0.18 nF/mm2 in the effective backside area of 71 mm2 suppressed dynamic IR drops in 10% and 59% for the single chip and four chip stack samples, respectively, during the operation of a 3.9 M-gate crypto core at 30 MHz. On-chip power noise monitoring (OCM) was applied in these measurements. The 3-D BBM PDN also effectively reduces power side channel information leakage, which is evaluated by 14 × increase in the number of externally observed electromagnetic (EM) noise waveforms to attain the t-test value of larger than 4.5. [ABSTRACT FROM AUTHOR]

This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a serious security hole that allows emerging backside physical security attacks. The proposed backside buried metal (BBM) structure forming a meander wire pattern on the Si-backside detects unexpected disconnection of the meander and warns the malicious attempts to expose a vulnerable Si substrate. Moreover, the BBM meander also shields key information of cryptographic circuit from both passive side-channel attacks and active laser fault injection as well. Unlike other conventional laminate-based protection, this backside monolithic approach does not require frontside wiring resources or additional packaging layers, resulting in only 0.0025% size-overhead. The BBM meander was formed on the backside of a 0.13- $\mu \text{m}$ CMOS cryptographic chip by wafer-level via-last BBM processing. [ABSTRACT FROM AUTHOR]

The 3-D-stacked large-scale integration (3-D-LSI) chips provide densely integrated capacitance and low impedance in vertically and horizontally distributed power delivery networks. This paper proposes a 3-D-LSI with superior electromagnetic interference (EMI) characteristics. A three-tier 3-D-LSI demonstrator integrated with through-silicon vias is manufactured. Self-interfering EMI suppression characteristics are captured by an embedded in-stack monitoring system and explained by a simple lumped component model including the entire test structure. Electromagnetic leakage, which affects other devices, is also characterized by the model. Chip evaluation and the model show good EMI characteristics, which arise from local shunting by a vertically integrated decoupling capacitor and from implicit capacitance. [ABSTRACT FROM AUTHOR]

Organic low- $k$ materials have been considered in the literature for satisfying the requirements of lowering the dielectric constant of the dielectric layer to decrease the problem of signal delay, lower power consumption, and to reduce cross talk between the neighboring paths, and lowering the fabrication temperature budget. In this paper, the feasibility of using Parylene-HT as a low-temperature deposition, high-uniformity coverage low-dielectric liner for copper-filled through-silicon vias (TSVs) in 3-D integration is investigated. In particular, the capability of embedding Parylene-HT in via-last fabrication process is validated through the demonstration of 100- \mu \text{m} -depth bottom-up copper-filled TSVs. TSVs with Parylene-HT as a liner were realized through vias etching, parylene vapor deposition, and copper electroplating processes. The Parylene-HT deposition and copper electroplating processes were implemented at room temperature, such that thermal-related issue would be avoided and device reliability would be enhanced. The insulation function of the Parylene-HT liner of the fabricated TSVs was characterized. Capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm2 at a field of 0.25 MV/cm were obtained through the measurement of the TSV arrays. The obtained results reveal the possibility of using such a high potential parylene in low-temperature budget 3-D integration applications. [ABSTRACT FROM PUBLISHER]

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of through-silicon via (TSV) bus driver/receiver cells are impacted by die thinning. While die thinning limits the ability for heat to diffuse into the wafer, it can also decrease the capacitance of the TSV which in turn decreases the driver׳s power, leading to an overall lower working temperature in some circumstances. In this work we have investigated the thermal effects of stacking 2–8 thinned ICs with TSVs, over a range of die thicknesses from 100 μ m to 25 μ m . Decreasing the die thickness from 100 μ m to 50 μ m provided the best balance with a 20% reduction in bus power at a cost of less than a 2% increase in driver temperature for all cases between 2 and 8 tiers. [ABSTRACT FROM AUTHOR]