1. Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation.
- Author
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Arimura, H., Dekkers, H., Ragnarsson, L.-A., Mitard, J., De Heyn, V., Mocuta, D., Collaert, N., Horiguchi, N., Cott, D., Boccardi, G., Loo, R., Wostyn, K., Witters, L., Conard, T., Suhard, S., and van Dorp, D.
- Subjects
ELECTRON mobility ,RELIABILITY in engineering ,DRY cleaning ,SURFACE preparation ,ON-chip charge pumps ,LOGIC circuits ,ANNEALING of metals - Abstract
This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-k last process. SiO
2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Six )Ge1-x Oy , which is, compared to a pure SiO2 , more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced DIT , and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum VOV of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm-Lg n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack. [ABSTRACT FROM AUTHOR]- Published
- 2019
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