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A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D nand Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide–nitride–oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (\4F^2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = \45 \ \nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = \45 \ \nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, we provide evaluation of memory stacks with La, Lu and Gd aluminates as charge trapping materials. Critical integration issues are pointed out, particularly the mixing of these materials with adjacent layers. It is found that, in order to control the mixing of the aluminates with the tunnel oxide, nitride (for Gd) or nitride+oxide (for La and Lu) buffer layers have to be used. The nitride buffer layer, however, mixes with the tunnel oxide during stack fabrication. This results in very good erase and endurance performance, which is attributed to enhanced hole tunneling from the Si substrate, but degrades the retention performance. [Copyright &y& Elsevier]