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Our study investigates differences in sensitivity of dry and wet environment in the field of biosensing experiment in detail and depth. The sensitivity of biosensing varies by means of surrounding conditions of silicon nanowire field effect transistor (SiNW FET). By examining charged polymer reaction in the silicon nanowire transistor (SiNW), we have discovered that the threshold voltage (V(T)) shift and change of subthreshold slope (SS) in wet environment are smaller than that of the air. Furthermore, we analyzed the sensitivity through modifying electrolyte concentration in the wet condition, and confirmed that V(T) shift increases in low concentration condition of phosphate buffered saline (PBS) due to the Debye length. We believe that the results we have found in this study would be the cornerstone in contributing to advanced biosensing experiment in the future.

This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 10(5) times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 10(5) with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density.

A porphyrin-silicon nanowire (Si-NW) hybrid field-effect transistor is introduced. The hybrid device has separate electrical and optical gates surrounding the Si-NW channel. Porphyrin, a component of chlorophyll, is employed as an optical gate to modulate the potential of the Si-NW channel. Due to the independently formed hybrid gates, both optical and electrical excitation can effectively modulate the device. The exposed porphyrin optical gate responds to the optical excitation, and independently formed electrical gates respond to the electrical excitation. Charge transfer characteristics between a semiconductor channel and the porphyrin optical gate are deeply investigated. Optical, electrical, and opto-electrical excitation methods are employed to analyze the charging and discharging behaviors. Of these methods, opto-electrical excitation enables the strongest charge transfer because the inversion electron formation by an electrical pulse and the photoinduced charge transfer by an optical stimulus are affected simultaneously. Discharging processes, such as rapid discharging, exponential detrapping, and the formation of metastable states are also analyzed.

A thermo-morphic transition of a silicon nanowire (Si-NW) is investigated in vacuum and air ambients, and notable differences are found under each ambient. In the vacuum ambient, permanent electrical breakdown occurs as a result of the Joule self-heating arising from the applied voltage across both ends of the Si-NW. The resulting current abruptly declines from a maximum value at the breakdown voltage (V(BD)) to zero. In addition, the thermal conductivity of the Si-NW is extracted from the V(BD) values under the vacuum ambient and shows good agreement with previously reported results. While the breakdown of the Si-NW does not exhibit negative differential resistance under the vacuum ambient, it interestingly shows negative differential resistance with multiple resistances in the current-voltage characteristics under the air ambient, similar to the behavior of carbon nanotubes. This behavior is triggered by current-induced oxidation, which leads to the thermo-morphic transition observed by TEM analyses. Additionally, the current-induced oxidation is favorably applied to reduce the size of a Si-NW at a localized and designated point., (© 2012 American Chemical Society)

A conductance-controllable hybrid device that utilizes the photoinduced charge transfer behavior of a porphyrin in a field-effect transistor (FET) with a nanogap is proposed and analyzed. A conventional metal-oxide-semiconductor (MOS) structure is modified to form a nanogap in which the porphyrin can be embedded. The conductance of an inversion channel is controlled by the negatively charged, optically activated porphyrin molecules. The proposed nanogap-formed MOSFET structure solves the conventional dilemma that a top-gate cannot be used for an organic-inorganic hybrid device because the top-gate blocks an entire area of a channel where organic material should be immobilized. The top-gate structure has much practicality compared with the back-gate structure because each device can be controlled individually. Furthermore, the device is highly compatible with the chip-based integrated system because the fabrication process follows the standard complementary metal-oxide-semiconductor (CMOS) technology. The charge transfer mechanisms between silicon and porphyrin are analyzed using devices with different doping polarities and geometrical parameters. The results show that the influence of the negative charge of the porphyrin in the device is reversed when opposite doping polarities are used. The device characteristics can be comprehensively evaluated using the energy band diagram analysis and simulation. The possible application of the proposed device for nonvolatile memory is demonstrated using the optical charging and electrical discharging behavior of the porphyrins., (© 2011 American Chemical Society)

Through the fusion of electrostatics and mechanical dynamics, we demonstrate a transformable silicon nanowire (SiNW) field effect transistor (FET) through a wafer-scale top-down approach. By felicitously taking advantage of the proposed electrostatic SiNW-FET with mechanically movable SiNWs, all essential logic gates, including address decoders, can be monolithically integrated into a single device. The unification of various functional devices, such as pn-diodes, FETs, logic gates, and address decoders, can therefore eliminate the complex fabrication issues associated with nanoscale integration. These results represent a step toward the creation of multifunctional and flexible nanoelectronics.

Abstract Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and −94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K2 at room temperature.

In this study, silicon nanowire (SiNW) FET-based and SiNW tunnel FET (TFET)-based biosensors are co-integrated with CMOS circuits by using top-down approached and CMOS-compatible back-end process simultaneously. The possibility of multiplexed sensing is verified with the fabricated FET and TFET biosensors. For multiplexed-sensing, two separate sensing materials which react with two distinct bio-targets are formed by partially capping the gold on SiO2 film through a lift-off process. Then two bio-receptors which selectively combine to the gold and the SiO2 are deposited. After the reaction of each biomolecule to each receptor, the changes of saturation and gate-induced-drain-leakage (GIDL) currents are monitored in the FET sensor. It is experimentally confirmed that two different biomolecules are independently detectable by the changes of the saturation and the GIDL currents in the FET sensor. To solve the dependence of the gold formation position on the sensitivity as well as the large current difference between the saturation and the GIDL currents, we demonstrated the TFET biosensor which uses the changes of tunneling and ambipolar currents generated in the source and the drain end. As a result, it is clearly revealed that two different biomolecules can be detected without interference, regardless of the position of the gold layer by the changes of the tunneling and the ambipolar currents with almost equivalent sensing current level. [ABSTRACT FROM AUTHOR]

In this paper, we fabricated In0.53Ga0.47As-on insulator (OI) MOSFETs on Si substrates with different doping types to mimic ground plane doping using direct wafer bonding and epitaxial lift-off (ELO) techniques. We investigated the impact of doping types on the ground plane and the backgate biasing, which are important and preferable components in monolithic 3-D (M3D) integration, on the electrical properties of MOSFETs, such as the threshold voltage ( ${V} _{T}$ ) and the effective mobility ( $\mu _{\textsf {eff}}$ ). It was found that ${V} _{T}$ and $\mu _{\textsf {eff}}$ were significantly modulated by the backsubstrate doping and the backbiasing. These observations were explained by the change of carrier distributions, which were confirmed by technology computer-aided design simulation. Furthermore, we investigated the reusability of InP donor substrates for sequential epitaxial growth after ELO process toward a cost-effective M3D integration with the In0.53Ga0.47As channel. [ABSTRACT FROM AUTHOR]

Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III–V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. This method provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OI metal-oxide-semiconductor field-effect-transistors fabricated through the proposed DWB and ELO. [ABSTRACT FROM PUBLISHER]

A simulation method for the electrolyte–insulator–semiconductor field-effect transistor (EISFET)-type sensor is proposed based on a well-established commercialized semiconductor 3-D technology computer-aided design simulator. The proposed method relies on the fact that an electrolyte can be described using a modified intrinsic semiconductor material because of the similarity between the electrolyte and the intrinsic semiconductor. The electrical double layer of the electrolyte is characterized in the simulation using the Gouy–Chapman–Stern model. Using the proposed simulation method, we extract the Debye lengths depending on phosphate buffered saline solutions with various concentrations and demonstrate that it is possible to simulate the screening effect. Furthermore, we investigate the responses of the EISFET-type silicon nanowire pH sensor based on our simulation method, which shows good agreement with the reported Nernst limit value. [ABSTRACT FROM PUBLISHER]

We investigate the performance of accumulation (ACC)-mode and inversion (INV)-mode silicon nanowire (SiNW) pH sensors that are electrically controlled by a liquid gate. The two sensing parameters of the changes of threshold voltage and current are explored in both types of SiNW pH sensors at different pH levels. As device dimensions and channel doping concentration increase, the performance of the ACC-mode biosensor degrades more rapidly than the performance of the INV-mode biosensor. Therefore, INV-mode SiNW pH sensors with a liquid gate could be robust to process variation and provide improved current sensitivity. [ABSTRACT FROM PUBLISHER]

A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW. [ABSTRACT FROM PUBLISHER]

This paper experimentally investigates the unique behavior of transconductance (gm) in the Schottky-barrier metal–oxide–semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of gm is observed. Thus, gm can be used as a novel metric that exhibits the transition of the carrier injection mechanisms from a thermionic emission (TE) to thermally assisted tunneling (TU) in the SB-MOSFETs. When the local maximum point of gm is observed, it can be expected that an incomplete transition occurs between TE and TU in SB-MOSFETs. When a dopant-segregation (DS) technique is implemented in the SB-MOSFETs, however, the carrier injection efficiency from the source to the channel is significantly improved, although the SBH is not minimized. As a consequence, the peculiar shape of the gm disappears, i.e., a complete transition from TE to TU can be enabled by the DS technique. [ABSTRACT FROM AUTHOR]

A dopant-segregated Schottky barrier (DSSB) Fin-FET silicon-oxide-nitride-oxide-silicon (SONOS) for NOR-type Flash memory is successfully demonstrated. Compared with a conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp dopant segregated Schottky contact at the source side can generate hot electrons, and it can be used to provide high injection efficiency at low voltage without any constraint on the choice of the proper gate and drain voltage. The DSSB FinFET SONOS device is therefore a promising candidate for NOR-type Flash memory with high-speed and low-power programming. [ABSTRACT FROM AUTHOR]

The effect of streptavidin concentration as a target molecule on the subthreshold swing (SS) of biotin-functionalized silicon nanoribbon sensors was investigated for a configuration of field effect transistors. The increasing concentration of conjugated target molecules was modeled as a degradation of the coupling capacitance between the electrolyte and the sensor surface. A binding factor for the ratio of conjugation between targets and receptors was modeled as a coupled capacitance and experimentally determined to be from 0.65 (streptavidin at 1 pM) to 1 (1 nM). This result suggests that SS is potentially a good indicator of the target concentration. [ABSTRACT FROM AUTHOR]

The unidirectional read-out characteristics of a two-terminal biristor are investigated through numerical simulations and experiments. The base doping profile in the biristor, which is analogous to an open-base bipolar junction transistor (BJT), is a key parameter to control both the multiplication factor and the common–emitter gain of the open-base BJT. The simulated results indicate that the asymmetric base doping produces a difference in the latch-up voltage according to the reading direction. A unidirectional conduction path is thereby implemented in a crossbar-array configuration that consists of only the two-terminal biristor. The experimental results based on a vertical structure with local charge injection support that the leakage path through the reverse read direction can be blocked by the asymmetric base doping structure with the selection of proper bias conditions. [ABSTRACT FROM PUBLISHER]

A junctionless transistor with a width of 10 nm and a length of 50 nm is demonstrated for the first time. A silicon nanowire (SiNW) channel is completely surrounded by a gate, and the SiNW is built onto the bulk substrate. The proposed junctionless transistor is applied to a Flash memory device composed of oxide/nitride/oxide gate dielectrics. Acceptable memory characteristics are achieved regarding the endurance, data retention, and dc performance of the device. It can be expected that the inherent advantages of the junctionless transistor can overcome the scaling limitations in Flash memory. Hence, the junctionless transistor is a strong candidate for the further scaling of nand Flash memory below the 20-nm node. [ABSTRACT FROM AUTHOR]

A gate length of 25 nm and a silicon nanowire (SiNW) with a width of 6 nm and a height of 10 nm fully surrounded by a gate are demonstrated. A suspended SiNW, which is fully depleted, is fabricated on a bulk substrate by employing the deep reactive-ion etching process known as the Bosch process. The electrical characteristics and short-channel effects (SCEs) of the SiNW MOSFETs with all-around gates are presented. The fabricated devices show excellent immunity against SCEs despite their being built on a bulk substrate and having gate lengths scaled down to the 25-nm regime. Improved electrostatic characteristics that suppress the SCEs are shown when the dimension of the SiNW is reduced. [ABSTRACT FROM AUTHOR]

We experimentally investigate the sensitivity of threshold voltage (VT) to the variation of silicon nanowire (SiNW) width (W \rm si) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors. [ABSTRACT FROM AUTHOR]

In the biological neural network, the learning process is achieved through massively parallel synaptic connections between neurons that can be adjusted in an analog manner. Recent developments in emerging synaptic devices and their networks can emulate the functionality of a biological neural network, which will be the fundamental building block for a neuromorphic computing architecture. However, on-chip implementation of a large-scale artificial neural network is still very challenging due to unreliable analog weight modulation in current synaptic device technology. Here, we demonstrate a binarized neural network (BNN) based on a gate-all-around silicon nanosheet synaptic transistor, where reliable digital-type weight modulation can contribute to improve the sustainability of the entire network. BNN is applied to three proof-of-concept examples: (1) handwritten digit classification (MNIST dataset), (2) face image classification (Yale dataset), and (3) experimental 3 × 3 binary pattern classifications using an integrated synaptic transistor network (total 9 × 9 × 2 162 cells) through a supervised online training procedure. The results consolidate the feasibility of binarized neural networks and pave the way toward building a reliable and large-scale artificial neural network by using more advanced conventional digital device technologies. [ABSTRACT FROM AUTHOR]