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In this letter, a Ni-Al alloy based metal induced lateral crystallization (MILC) process in a vertical Si channel, from 3-D NAND flash cell, is reported. Alloying Ni with Al improves NiSi2 nucleation, resulting in a favorable channel morphology after the silicide transport. We show that it is possible to achieve better ON-current and gate control over the existing Ni-only MILC process with no observable impact on the memory performance. [ABSTRACT FROM AUTHOR]

The ferroelectric (FE)-HfO2-based field-effect transistor (FEFET) is a promising candidate for emerging memory. However, data retention (DR) loss has been flagged as a key issue. Although two models of DR loss in FEFET have been proposed—the charge trapping model and the depolarization model—it is difficult to separate the dominant cause. In this article, simultaneous ${P}$ – ${V}$ and ${I}$ – ${V}$ measurements are performed which enable separation of these mechanisms. Different behavior of polarization and threshold voltage loss and recovery in a “set” state between two types of FEFET structures, metal (TiN)/FE-HfO2/SiO2/Si substrate (MFIS) and metal (TiN)/Si/FE-HfO2/SiO2/Si-substrate (MSFIS), clarify that the dominant mechanism of the DR loss in both structures is different. In addition, the impact of external bias and interfacial layer (IL) on the DR loss is revealed: the polarization loss is strongly affected by the external bias in both types of FEFET, indicating effective work function (eWF) has a strong impact on depolarization. On the other hand, the thickness and processing of IL strongly impact the charge trapping characteristics. Based on our understanding, excellent improvement of the DR is achieved: memory window ~0.8 V at 85 °C, extrapolated to ten years. [ABSTRACT FROM AUTHOR]

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D nand Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide–nitride–oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (\4F^2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = \45 \ \nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = \45 \ \nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, we provide evaluation of memory stacks with La, Lu and Gd aluminates as charge trapping materials. Critical integration issues are pointed out, particularly the mixing of these materials with adjacent layers. It is found that, in order to control the mixing of the aluminates with the tunnel oxide, nitride (for Gd) or nitride+oxide (for La and Lu) buffer layers have to be used. The nitride buffer layer, however, mixes with the tunnel oxide during stack fabrication. This results in very good erase and endurance performance, which is attributed to enhanced hole tunneling from the Si substrate, but degrades the retention performance. [Copyright &y& Elsevier]