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Start Over Author "Adir, Allon" Topic silicon
2 results on '"Adir, Allon"'

1. Leveraging Pre-Silicon Verification Resources for the Post-Silicon Validation of the IBM POWER7 Processor.

Author

Adir, Allon, Nahir, Amir, Shurek, Gil, Ziv, Avi, Meissner, Charles, and Schumann, John

Subjects
SILICON, SYNERGETICS, INTEGRATED circuit verification, COMPUTER input-output equipment, CENTRAL processing units
Abstract

The growing importance of post-silicon validation in ensuring functional correctness of high-end designs has increased the need for synergy between the pre-silicon verification and post-silicon validation. This synergy starts with a common verification plan. It continues with common verification goals and shared tools and techniques. This paper describes our experience in improving this synergy in the preand post-silicon verification of IBM's POWER7 processor chip and by leveraging pre-silicon methodologies and techniques in the post-silicon validation of the chip. [ABSTRACT FROM AUTHOR]

Published
2011

2. Concurrent Generation of Concurrent Programs for Post-Silicon Validation.

Author

Adir, Allon, Nahir, Amir, and Ziv, Avi

Subjects
*SILICON, *INTEGRATED circuits, *MULTIPROCESSORS, *CONCURRENT engineering, *SIMULTANEOUS multithreading processors, *TIMING circuits, *HARDWARE
Abstract

The continuing trend toward increased parallelism in processor design can be seen in both the growing number of processor cores per system and in on-core hardware mechanisms that assist parallelism, such as multithreading and cache hierarchies. This complexity exacerbates the problem of ensuring the functional correctness of such hardware systems. The growing importance of post-silicon validation is leading to an emerging type of parallel application, namely, the hardware exerciser. We describe a method for exercising parallel hardware by generating pseudorandom concurrent test programs. The test generation is carried out on the tested parallel platform and thus the generator itself is also a concurrent program. We describe the challenges associated with this technology and the approach used by the Threadmill hardware exerciser, a tool developed for the post-silicon validation of the IBM POWER7 processor. [ABSTRACT FROM AUTHOR]

Published
2012
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