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This article presents a $4\times $ time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s, $208\times $ oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB. [ABSTRACT FROM AUTHOR]

This article presents a split time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) with digital background timing-skew mismatch calibration. It divides a TI-SAR ADC into two split parts with the same overall sampling rate but different numbers of TI channels. Benefitting from the proposed split TI topology, the timing-skew calibration convergence speed is fast without any extra analog circuits. The input impedance of the overall TI-ADC remains unchanged, which is essential for the preceding driving stage in a high-speed application. We designed a prototype seven-/eight-way split TI-ADC implemented in 28-nm CMOS. After a digital background timing-skew calibration, it reaches a 54.2-dB signal-to-noise-and-distortion ratio (SNDR) and 67.1-dB spurious free dynamic range (SFDR) with a near Nyquist rate input signal and a 2.5-GHz effective resolution bandwidth (ERBW). Furthermore, the power consumption of ADC core (mismatch calibration off-chip) is 12.2-mW running at 1.6 GS/s, leading to a Walden figure-of-merit (FOM) of 18.2 fJ/conv.-step and a Schreier FOM of 162.4 dB, respectively. [ABSTRACT FROM AUTHOR]

This brief presents a uniform quantization theory (UQT)-based digital-to-analog converter (DAC) linearity calibration for a successive approximation register (SAR) analog-to-digital converter. According to the uniform quantization noise property, the nonlinearity due to the parasitics in an LSB array of the split-DAC structure is estimated and corrected in the digital domain. The calibration requires that the characteristic of the input signal must fulfill the prerogative of the quantization theory. The advantages lie in its low design complexity with no additional analog circuit modification. The proposed calibration is verified by both behavioral simulations and measured results in an SAR ADC. The measurements are based on a prototype implemented with large nonlinear split-DACs, which demonstrate that the UQT-based linearity calibration can effectively improve the Signal to Noise and Distortion (SNDR) from 56.9 to 63.3 dB at dc input with a sampling frequency of 120 MS/s. [ABSTRACT FROM PUBLISHER]

This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is discussed, and the possible limits caused by nonidealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65-nm CMOS prototype operating at 160 MS/s and 1.1-V supply show an SNDR of 55.4 dB and 2.72 mW total power consumption. [ABSTRACT FROM PUBLISHER]