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The Belle II experiment located at KEK, Japan takes data from asymmetric e + e − collision provided by the SuperKEKB accelerator. The Silicon Vertex Detector (SVD), which is part of the Belle II Vertex Detector (VXD), has been operating smoothly and reliably since the start of data taking in March 2019. In this article, we report on the performance of the SVD in terms of the large signal-to-noise ratio, the good hit position resolution as well as the good hit-time resolution. New algorithms based on hit-time information are under development to improve robustness of tracking performance within the anticipated high background environment. The Background situation of the SVD has been constantly monitored and no degradation in performance is observed so far. To investigate the SVD performance at high luminosity runs in the future, simulation as well as an irradiation campaign are launched and their results are summarized. During the first long shutdown of the Belle II experiment, which starts from June 2022, the VXD has been refurbished with a new two-layer DEPFET pixel detector located inside the SVD. All the delicate phases of the disassembly, re-assembly and installation of the new VXD have been successfully completed. The new VXD commissioning phase began in Sept 2023 to get ready for beam operation starting in early 2024. [ABSTRACT FROM AUTHOR]

The Belle II experiment is taking data at the asymmetric SuperKEKB collider (KEK, Japan), which operates at the Υ (4 S) resonance. The vertex detector is composed of an inner two-layer pixel detector (PXD) and the silicon vertex detector (SVD), made of four layers of double-sided silicon strip detectors. A deep knowledge of the system has been gained since the start of operations in 2019 by assessing the high-quality and stable reconstruction performance of the detector. The very high hit efficiency and large signal-to-noise ratio are monitored via online data-quality plots. The good cluster-position resolution is estimated using the unbiased residual with respect to the track, and it is in reasonable agreement with the expectations. The SVD dose is estimated by the correlation of the SVD occupancy with the dose measured by the diamond sensors of the radiation-monitoring and beam-abort system. First radiation damage effects are measured on the sensor current and strip noise are shown not to affect the performance. Six samples of the shaped particle signal are recorded utilizing the multi-peak mode of the APV25 front-end chip and used to determine the hit timing with a precision of 2 to 3 ns. Recently a method to compute the time of collision from SVD hit time information has been implemented and verified with simulations and on data. [ABSTRACT FROM AUTHOR]

A silicon vertex detector (SVD) for the Belle-II experiment comprises four layers of double-sided silicon strip detectors (DSSDs), assembled in a ladder-like structure. Each ladder module of the outermost SVD layer has four rectangular and one trapezoidal DSSDs supported by two carbon-fiber ribs. In order to achieve a good signal-to-noise ratio and minimize material budget, a novel chip-on-sensor “Origami” method has been employed for the three rectangular sensors that are sandwiched between the backward rectangular and forward (slanted) trapezoidal sensors. This paper describes the bonding procedures developed for making electrical connections between sensors and signal fan-out flex circuits (i.e., pitch adapters), and between pitch adapters and readout chips as well as the results in terms of the achieved bonding quality and pull force. [ABSTRACT FROM AUTHOR]

Since the start of data taking in spring 2019 at the SuperKEKB collider (KEK, Japan) the Belle II Silicon Vertex Detector (SVD) has been operating reliably and with high efficiency, while providing high quality data: high signal-to-noise ratio, greater than 99% hit efficiency, and precise spatial resolution. These attributes, combined with stability over time, result in good tracking efficiency. Currently the occupancy, dominated by beam-background hits, is quite low (about 0.5 % in the innermost layer), causing no problems to the SVD data reconstruction. In view of the operation at higher luminosity foreseen in the next years, specific strategies aiming to preserve the tracking performance have been developed and tested on data. The time stability of the trigger allows reducing sampling of the strip-amplifier waveform. The good hit-time resolution can be exploited to further improve the robustness against the higher level of beam background. First effects of radiation damage on strip noise, sensor currents and depletion voltage have been measured: they do not have any detrimental effect on the performance of the detector. Furthermore, no damage to the SVD is observed after sudden and intense bursts of radiation due to beam losses. [ABSTRACT FROM AUTHOR]

The Silicon Vertex Detector (SVD) is a part of the vertex detector in the Belle II experiment at the SuperKEKB collider (KEK, Japan). Since the start of data taking in spring 2019, the SVD has been operating stably and reliably with a high signal-to-noise ratio and hit efficiency, achieving good spatial resolution and high track reconstruction efficiency. The hit occupancy, which mostly comes from the beam-related background, is currently about 0.5% in the innermost layer, causing no impact on the SVD performance. In anticipation of the operation at higher luminosity in the following years, two strategies to sustain the tracking performance in future high beam background conditions have been developed and tested on data. One is to reduce the number of signal waveform samples to decrease dead time, data size, and occupancy. The other is to utilize the good hit-time resolution to reject the beam background hits. We also measured the radiation effects on the full depletion voltage, sensor current, and strip noise caused during the first two and a half years of operation. The results show no detrimental effect on the SVD performance. [ABSTRACT FROM AUTHOR]

The Belle II experiment at the SuperKEKB collider of KEK (Japan) started recording physics data in spring 2019 with all its subdetectors installed and with the goal of accumulating 50 ab−1 of e + e − collision events at the unprecedented instantaneous luminosity of 8 × 1 0 35 cm − 2 s − 1 , about 40 times larger than its predecessor. The Belle II vertex detector plays a crucial role in the broad Belle II physics program, especially for time-dependent CP measurements. It consists of two layers of DEPFET-based pixels and four layers of double-sided silicon strip detectors (SVD). The experience gained from the first period of SVD operation can be summarized as smooth and reliable running of the detector, with high stability of noise levels and calibration parameters obtained from local calibration runs. No major problem has been experienced. The detector even survived a few serious radiation accidents in which the beam was lost due to failure in the machine focusing quadrupoles without any notable damage. The SVD performance were carefully studied with these first physics data. The SVD showed excellent hit and tracking efficiency. Moreover, cluster energy and signal to noise ratio as well as the hit time and spatial resolutions measured on data showed a fair agreement with the expected performance. • Belle II silicon vertex detector operated during the first year of the experiment. • All sensors worked with stable and excellent hit efficiencies above 99 %. • Signal-to-noise ratios between 15 and 30, cluster time resolution better than 3 ns. • First effects of irradiation visible in leakage currents. [ABSTRACT FROM AUTHOR]

This paper shows the hardware and the procedure utilized to test all components of the readout system (cables, FADC boards, junction boards) of the Belle II Silicon Vertex Detector after the series production. For the FADC board special testing hardware and firmware were designed and created to check all digital and analog inputs and outputs as well as all data interconnections on the board. The main FPGA on the FADC board generates digital signals which are converted to periodic analog differential alternating voltages up to 40 MHz on the FADC board tester, which then are fed into the analog inputs of the FADC board. Histograms and scans of the samples are recorded by using random equivalent-time sampling or sequential equivalent-time sampling, allowing to characterize the behavior of the system with a much higher bandwidth than the ADCs could do with conventional measurements. Small changes of parameters of the assembly (like using a cable of different length) lead to significant changes of the measured values, creating a sensitive testing instrument. The shapes of the distributions are analyzed and compared to references by software which then decides if a test is passed or not. The commissioning setup of the whole readout chain, with all the final components including the final detector, has been tested in three phases. The respective graphs of the signal-to-noise ratios of the strips of a detector module and histograms of the noise development of the whole detector show very high consistency of the SVD readout system. [ABSTRACT FROM AUTHOR]