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With the development of Artificial Intelligence (AI) and Binary neural networks (BNN), the computing efficiency of the computing system is expected to be much better, however, enormous amounts of data processing have caused an intolerable ‘memory wall’ and ‘power wall’ challenge for traditional Von Neumann architectures. Therefore, more advanced Computing-in-memory (CiM) architectures are proposed. The emerging non-volatile memory Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), with its fast access speed, near-zero leakage power consumption and high density is one of the most competitive carriers for CiM architectures.Due to the inherent read-write asymmetry of STT-MRAM, the read overhead is multiples smaller than the exaggerated write overhead. To better exploit the potential of MRAM, we focus on implementing an CiM based on the reading process.This work introduces the principle of CiM and proposes four basic logic operations (XNOR, XOR, AND and OR) based on STT-MRAM. Furthermore, a delay-based XNOR-popcount (XNOR-PC) operation for BNN based on XNOR operation is proposed. Incorporating the reading characteristics of STT-MRAM and slight modifications to the peripheral circuitry, these operations achieve significant optimisation in terms of performance and energy consumption. Simulation results show the proposed scheme can reduce the latency of XOR, AND, and OR operations at least by 99.3%, 82.2% and 80.2% compared with the existing design. The proposed XNOR-PC operation achieves at least a 59.4% reduction in power consumption and has a high degree of reliability. Also, Monte Carlo simulations prove the feasibility and robustness of the schemes. [ABSTRACT FROM AUTHOR]

High power issues have become the main drawbacks of CMOS logic circuits as technology node shrinks below 45 nm. Emerging spintronics nanodevices-based hybrid logic-in-memory architecture has recently been investigated to overcome these issues. Among them, spin-transfer-torque-based magnetic tunnel junction (STT-MTJ) nanopillar is one of the most promising spintronics nanodevices thanks to its nonvolatility, fast access speed, and 3-D integration with CMOS technology. However, hybrid STT-MTJ/CMOS logic faces severe reliability issues in ultradeep submicron technology nodes (e.g., 28 nm) due to the increasing process variations and reduced supply voltage. This paper presents architecture designs and comparative study of multicontext hybrid STT-MTJ/CMOS logic structures with a particular focus on reliability investigation. Their merits and shortcomings are demonstrated depending on the addressed applications. Finally, some design considerations and strategies are also presented to further optimize their reliability performance. Transient and Monte Carlo statistical analyses are performed by using an industrial CMOS 28-nm design kit and a physics-based STT-MTJ nanopillar compact model to exhibit their functionalities and effectiveness. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising candidate for the next-generation high-speed, low-power, and scalable nonvolatile memory technology. Its advantageous features have attracted much attention in the area of research and development, and a number of preindustrial prototypes and small-scale products have been demonstrated. One expects to widely commercialize it in the next few years. One of the critical issues that blocks STT-MRAM’s wide commercialization is its low sensing reliability due to the relatively small tunnel magnetoresistance ratio of the magnetic tunnel junction (MTJ) and the continuously increasing process variations, especially as technology process scales down to the deep submicrometer nodes (e.g., 40 nm). In this paper, we present a variation-tolerant high-reliability sensing circuit for deep submicrometer STT-MRAM. This circuit, using triple-stage sensing and charge transfer amplification, is able to tolerate significantly the process variations and improve greatly the sensing margin by sacrificing some sensing time. Using a CMOS 40 nm design kit and a precise STT-MTJ compact model, transient and Monte Carlo simulations have been carried out to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) embedded in complementary metal–oxide–semiconductor (CMOS) has been considered as one of the potentially powerful solutions to build up nonvolatile memory and logic circuits. It possesses many intrinsic merits, such as high speed, instant on/off, good scalability and low-leakage power, and promises to extend the Moore's law. A critical issue in this hybrid MTJ/CMOS structure is the reliable integration of MTJ electric signals to CMOS electronics, especially for the deep submicrometer technology nodes (e.g., 28 nm) in presence of low supply voltage and serious process variations. In this paper, we propose a new sensing amplifier, named separated precharge sense amplifier. This circuit, by separating the discharging and evaluation stages of the sensing operation, can operate at a lower supply voltage (<1.0~V) and reduces the effects of process variations as technology scales, thereby providing higher sensing reliability compared with the previously proposed solutions while preserving the high-speed and low-power consumption. Transient and Monte-Carlo statistical simulations are performed to demonstrate its sensing performance. [ABSTRACT FROM AUTHOR]

Power issues have become a major problem of CMOS logic circuits as technology node shrinks below 90 nm. In order to overcome this limitation, emerging logic-in-memory architecture based on nonvolatile memories (NVMs) are being investigated. Spin transfer torque (STT) magnetic random access memory (MRAM) is considered one of the most promising NVMs thanks to its high speed, low power, good endurance, and 3-D back-end integration. This paper presents a novel magnetic full-adder (MFA) design based on perpendicular magnetic anisotropy (PMA) STT-MRAM. It provides advantageous power efficiency and die area compared with conventional CMOS-only full adder (FA). Transient simulations have been performed to validate this design by using an industrial CMOS 40 nm design kit and an accurate STT-MRAM compact model including physical models and experimental measurements. [ABSTRACT FROM PUBLISHER]