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The abilities to fabricate wafer scale single crystalline oxide thin films on metallic substrates and to locally engineer their resistive switching characteristics not only contribute to the fundamental investigations of the resistive switching mechanism but also promote the practical applications of resistive switching devices. Here, wafer scale LiNbO3 (LNO) single crystalline thin films are fabricated on Pt/SiO2/LNO substrates by ion slicing with wafer bonding. The lattice strain of the LNO single crystalline thin films can be tuned by He implantation as indicated by XRD measurements. After He implantation, the LNO single crystalline thin films show self-rectifying filamentary resistive switching behaviors, which is interpreted by a model that the local conductive filaments only connect/disconnect with the bottom interface while the top interface maintains the Schottky contact. Thanks to the homogeneous distribution of defects in single crystalline thin films, highly reproducible and uniform self-rectifying resistive switching with large on/off ratio over four order of magnitude was achieved. Multilevel resistive switching can be obtained by varying the compliance current or by using different magnitude of writing voltage. [ABSTRACT FROM AUTHOR]

Wafer level metal bonding involving copper layers is a key technology for three-dimensional integration. An appropriate surface activation can be performed in order to obtain room temperature direct bonding with bonding strength to be compatible with microelectronic device integration. In this paper, we focus on bonding strengthening mechanisms in the low temperature range from 20 to 100 °C. In order to improve the bonding interface closure, several process parameters are studied: water amount available when surfaces are brought into contact and copper layers deposition technique have been identified to be predominant in this low temperature range. Based on metal oxidation theory, several mechanisms are proposed and some calculations on this bonding strengthening are performed. For the first time, activation energies of this phenomenon are obtained for copper layers deposited by different method in the specific environment of the bonding interface. This study gives guidelines and recommendations for the integration of this metal bonding technique at low temperature. [ABSTRACT FROM AUTHOR]

This paper presents the vacuum wafer level packaging of in-house manufactured two-dimensional micro- mirrors based on the electrostatic driving principle, fabricated using a bulk technology on bonded-silicon-on-insulator wafers. The so called buried signal line concept is used in order to obtain a wafer bond friendly bonding frame. Two versions of the buried signal line concept are described in the paper: crystalline Si and poly-Si based. Anodic and glass frit bonding methods were used to bond a stack of four wafers, resulting in a vacuum-sealed package. The fabrication technology, alignment, bonding, dicing and electrical characterization are discussed. A vacuum level of 120 Pa with no getter materials was reached in the package. Due to vacuum packaging the driving voltage of the micro-mirrors after dicing could be significantly decreased from approximately 170 V to less than 35 V. [ABSTRACT FROM AUTHOR]

Silicon direct wafer bonding is a process with many application areas. Depending on the application, perfect insulation or negligible resistance is desired across the bonded interface. We have investigated the resistivity of hydrophilic high-temperature silicon direct wafer bonds by measuring the resistance across bonded frames suitable for device encapsulation. Frame widths of 100, 200, and 400 µm were fabricated. Hydrophilic pre-bonded laminates resulted in strong bonds and a dicing yield above 89 % for frame widths of 200 µm or wider. The average resistance of dies from boron implanted laminates was 0.35-0.44 Ω, and the average resistance of dies from un-implanted laminates was 0.51-0.68 Ω. All resistances were independent of the bonding area, showing that the resistance of the bonded interface was negligible. Dies from boron implanted wafers had good Al-Si contacts and lower standard deviation of the resistance, indicating that the implantation improved the reliability of the electrical contacts. In the case of boron implanted laminates, the low resistance is explained by a discontinuous SiO and areas with continuous silicon lattice at the bonded interface. The results show that the oxide formed during silicon-silicon direct wafer bonding is broken up during bond annealing for 2 h at 1,050 °C, forming electrical connections of high quality between the two bonded wafers. [ABSTRACT FROM AUTHOR]

The use of reconstructed silicon wafers obtained after high temperature annealing under H atmosphere was demonstrated as an efficient way for increasing the bonding energy of silicon hydrophobic bonding (Rauer et al. ). Mechanisms occurring in these bondings are the focus of this paper. Si bonding interface closure was analyzed at the nanometer scale using X-Ray Reflectivity and Fourier Transform InfraRed spectroscopy in multiple internal reflexion mode. These two characterization techniques enable one to follow the interface closure taking under consideration mechanical and chemical aspects. We have shown that the terrace morphology and the monohydride surface termination specific to reconstructed Si surfaces both play a role in obtaining an efficient bonding gap closure after annealing at low temperature. [ABSTRACT FROM AUTHOR]

Component miniaturization is increasingly gaining importance in numerous microsystem technologies, including medical technology, biotechnology, and drive technology. In this study, two types of nano-sized powder, namely, metal (stainless steel 316L) and ceramic (yttria-stabilized zirconia), were used to fabricate miniature parts through micro powder injection molding. Micro parts were produced by mixing powders with a binder system, followed by injection, debinding, and sintering process. Partially water-soluble binder system with surfactant addition was used to mix with either stainless steel 316L or yttria-stabilized zirconia nanopowder to form feedstock to avoid the agglomeration of fine powder and environmentally hazardous organic binder. The polyethylene glycol loss in water was observed after a rapid removal period in the first 60 min of immersion for the micro parts. Approximately 99 % of the polymethyl methacrylate binder was removed after pyrolysis at 450 °C for 2.5 h. Sintered ceramic and metallic parts showed a relative density that is approximately 97 % of theoretical density and free of defects. Hardness of approximately 221 and 1,200 Hv was achieved for the fabricated micro parts using stainless steel 316L and yttria-stabilized zirconia powders, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a fabrication process for micro synthetic jet actuators (SJA) by bonding a high-quality Pb (Zr,Ti) O (PZT) ceramic wafer to a silicon wafer using epoxy resin at low temperature (<150 °C). The bulk-PZT was lapped and polished to be PZT thick film by chemical mechanical polishing (CMP) method, and patterned by wet-etching method. The cavity and orifice of SJA were formed by inductive coupled plasma etching (ICP) method. A MEMS piezoelectric SJA was then completed and characterized, including the performance of the PZT thick film. While the dimension of bonded PZT thick film is about 6,000 × 6,000 × 100 μm, and the dimension of Si membrane is about 1,000 × 1,000 × 20 μm. The experimental results show that the maximum center amplitude of PZT-Si diaphragm is 15.05 μm at Vp-p of 90 V and the resonant frequency of 5 kHz, and the maximum jet velocity is higher than 11 m/s. This novel process has great potential to fabricate MEMS piezoelectric synthetic jet actuators. [ABSTRACT FROM AUTHOR]

In this study we proposed a device composed of dry electrode and dry adhesive medical patch for biopotentials measurement. The behavior of the dry adhesive with mushroom-shaped micropillars is characterized through normal and friction force test. The adhesion strength (~1.2 N/cm) is comparable to acrylic medical patch, and the repeating cycle testing result demonstrates that the adhesion strength of dry adhesive medical patch is larger than that of acrylic medical patch. Moreover, the dry adhesive medical patch does not cause skin to turn allergic owning to its biocompatibility. The proposed device also is used to record electrocardiogram (ECG) with dry electrode. Compared with conventional wet electrode, the signal quality is outstanding. The QRS-complex and T-wave of ECG are clearly legible. [ABSTRACT FROM AUTHOR]

A new technique was developed for embossing microstructures on thermoplastic substrates, which can achieve high accuracy replication with little loss of the production efficiency. The technique is no need of the preheating process and cooling device. In the new technique, just the surface layer of the polymer substrate was heated through heat transmission and ultrasonic viscoelastic heating was the major heat source. For our new technology, the temperature of the mould just provided the initial temperature of the mould-substrate interface and a higher boundary temperature for embossing. The replication accuracies of three embossing technologies were contrasted, including ultrasonic embossing at room temperature (HER), thermal assisted ultrasonic embossing (TUE) and local thermal assisted ultrasonic embossing (L-TUE). The results indicated that, the replication accuracy of L-TUE was approximate with TUE. Moreover, the effects of the processing parameters on the replication quality, including average replication depth and uniformity over the entire chip, were investigated. Different with our prediction, the replication accuracy did not monotonously improved with the ultrasonic force and the temperature of the mold. Finally, the temperature test was carried out to study the temperature characteristic of our new technology. [ABSTRACT FROM AUTHOR]

Two sapphire substrates are tightly bonded through a fresnoite-glass thin film, by irradiation with a 1,064 nm nanosecond laser. The composition of the glass solder at the bond interface changes, due to incorporation of Al from the upper substrate. The oxidic solder remains amorphous after laser irradiation, but after annealing (850 °C for 1 h) crystalline structures are observed in different morphologies, which are attributed not only to fresnoite, but also to Ba-Ti-Al-O phases, which lead to a strong luminescence of the laser irradiated region under UV excitation. [ABSTRACT FROM AUTHOR]

This paper deals with the improvement of the TTV values (Total Thickness Variation) of 300 mm silicon wafers thinned down at 100 μm using the ZoneBond (ZoneBond is registred by Brewer Science Inc.) technology. We have demonstrated that the thin film TTV of the film was mainly driven by the bonding process and was very tolerant towards the coating step. It was also shown that, within the experiment precision, the TTV value was not changed by the grinding thinning process. 8 µm was the best TTV value obtained after the optimization of the bonding parameters. [ABSTRACT FROM AUTHOR]

Direct bonding of InP dies to Si wafer at low temperature utilizing AlO high-κ dielectric as the interfacial material for homogeneous bonding is reported. The bonding technique is assisted with a UV/Ozone exposure for surface activation and the activation time is optimized for the various intermediate layer thicknesses (5, 10, 20 nm). After the pre-bonding stage, annealing is carried out at 300 °C for 3 h. A bonding interface with minimal interfacial voids is reported for low intermediate layer thickness. The bonding interfaces are examined and a homogeneously bonded interface is shown in the IR images as well as in the FIB micrographs. Additionally a heat transfer simulation is also carried out and the InP/AlO-AlO/Si bonded structure is shown to closely match the thermal characteristics of a direct bonding approach with no intermediate layer. A high quality bonding interface is revealed along with improved heat dissipation characteristic for AlO interface. Therefore, AlO proves to be an advantageous candidate for its use in potential Si photonic integrated circuits application. [ABSTRACT FROM AUTHOR]

This paper presents a new bonding procedure for thick silicon wafers. Those wafers are less flexible and have usually a larger wafer bow. That implicates that standard bonding techniques, such as silicon fusion bonding or anodic bonding, produce non satisfactory yield results. A compliant layer is required to overcome this problem. For the new bonding principle, silicon wafers are structured by a self-masking deep reactive ion etching process. Thereby a forming of needle-shaped nanostructures (known as Black Silicon) on the surface is generated. Between both wafers a green LTCC (low temperature cofired ceramic) foil was placed which assumes multiple functions. The foil is able to compensate the wafer bow, is easy to structure and leads to a quasimonolithic compound after pressure assisted sintering. In the paper the fabrication steps for bonding are explained in detail, especially the adjustment of flexible and unflexible substrates. The interface and the mechanical properties were analyzed and discussed. [ABSTRACT FROM AUTHOR]

SOI circuit exhibits excellent performance and rehabilitee but with the component miniaturization trend and the clock frequency increase, the self-heating phenomena that arise from the SOI structure itself must not be underestimated. In order to minimize this problem, several candidates have been identified to replace the buried silicon oxide (SiO) by high thermal conductive dielectric layers such as HfO, SiN, diamond or AlO. In order to elaborate a SOI structure using this kind of innovative buried dielectric, first of all, their direct bonding with silicon has to be studied. In this work, we investigate the bonding thermal behaviour of Si/AlO and AlO/AlO direct bonded structures: bondings are submitted to room temperature up to 900 °C annealing. Amorphous or crystallized AlO thin films were used in this study. Bonding energies are measured in an anhydrous atmosphere and bonding defectivity is analysed using scanning acoustic microscope (SAM). With amorphous a-AlO layer, for T > 200 °C, high bonding energy are obtained even if high defect density appeared when annealing temperature exceeded 400-500 °C. Spontaneous debonding phenomena even occurred for a-AlO/a-AlO direct bonding. This defectivity, unobservable using infrared camera, may be explained by chemical or structural AlO modification such as gases desorption, internal stress or crystallisation state. Bonding with crystallized AlO film has been also characterized by infrared spectroscopy and complementary analysis. No high defect density is observed with crystallized AlO layer. Based on these results, an AlO bonding mechanism is proposed. [ABSTRACT FROM AUTHOR]

Indium phosphide (InP) and gallium arsenide (GaAs) 100 mm wafers were bonded by direct wafer bonding in a cleanroom environment. Unexpected high bow values measured at room temperature after different thermal annealings are the focus of this study. Various experiments such as in situ bow measurements, surface XPS characterizations and TEM cross section observations highlight the key mechanisms that evolve with temperature. Over 200 °C, gallium oxide is formed at the bonded interface due to the presence of water that is trapped at the InP/GaAs interface during the hydrophilic bonding. These results allow us to explain the heterostructure debonding/re-bonding behavior. [ABSTRACT FROM AUTHOR]

Metal wafer bonding is a well-established technology in the semiconductor industry. This technology gains more and more importance due to increasing market demands, particularly for three-dimensional integrated circuits and integration of complementary metal oxide semiconductor and microelectromechanical systems devices used in consumer electronics. Cu-Cu wafer bonding at low temperature is a very attractive process which can be used for both mechanical joints and electrical interconnects in wafer-level processes. In order to facilitate a permanent Cu-Cu bond at low temperature-in contrast to a typical ~400 °C Cu-Cu bonding temperature-the effect of material properties and bonding parameters has to be understood well. Therefore a comprehensive characterization including both, namely surface and interface analysis before and after wafer bonding of non-patterned Cu layers, respectively, is required in order to optimize the Cu-Cu metal wafer bonding process. Low temperature Cu-Cu bonding, namely ≤200 °C, of ~500 nm sputter-deposited Cu films was demonstrated and characterized. Selected analytical methods, such as transmission electron microscopy, Auger electron spectroscopy and electron backscatter diffraction, and their corresponding specimen preparation techniques for microstructure and elemental composition evaluation are introduced. Experimental results of surfaces and interfaces investigation (materials properties with high impact on their bonding behavior), such as the (i) surface roughness, (ii) Cu native oxide, (iii) Cu (surface) purity and (iv) Cu grain size, as well as the influence of the (vi) bonding temperature are presented. [ABSTRACT FROM AUTHOR]

ABSTRACT Triple-junction solar cells from III-V compound semiconductors have thus far delivered the highest solar-electric conversion efficiencies. Increasing the number of junctions generally offers the potential to reach even higher efficiencies, but material quality and the choice of bandgap energies turn out to be even more importance than the number of junctions. Several four-junction solar cell architectures with optimum bandgap combination are found for lattice-mismatched III-V semiconductors as high bandgap materials predominantly possess smaller lattice constant than low bandgap materials. Direct wafer bonding offers a new opportunity to combine such mismatched materials through a permanent, electrically conductive and optically transparent interface. In this work, a GaAs-based top tandem solar cell structure was bonded to an InP-based bottom tandem cell with a difference in lattice constant of 3.7%. The result is a GaInP/GaAs//GaInAsP/GaInAs four-junction solar cell with a new record efficiency of 44.7% at 297-times concentration of the AM1.5d (ASTM G173-03) spectrum. This work demonstrates a successful pathway for reaching highest conversion efficiencies with III-V multi-junction solar cells having four and in the future even more junctions. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A new thermosetting polymer, modified poly (diallyl phthalate) (PDAP), is used as intermediate layer to realize a void-free wafer-level transfer bonding, in which the bonding interface contains patterned metal. Through glass–silicon bonding experiments, bonding defects are easily recognized with light microscopy. Three typical defect types are identified as: uneven flow defect, particle defect and bubble defect. The processing parameters, such as bonding pressure, pre-baking temperature, polymer thickness and coating conditions, have been optimized based on analysis of the defect formation. The optimized conditions have yielded a void-free wafer-level adhesive bonding. Then, the die shearing test indicates a good bonding strength. Additionally, the transfer bonding process is applied in SOI–silicon bonding as a practical example of MEMS fabrication. [ABSTRACT FROM AUTHOR]

This paper presents a MEMS energy harvesting device which is able to generate power from two perpendicular ambient vibration directions. A CYTOP polymer is used both as the electret material for electrostatic transduction and as a bonding interface for low-temperature wafer bonding. The device consists of a four-wafer stack, and the fabrication process for each wafer layer is described in detail. All the processes are performed at wafer scale, so that overall 44 devices can be fabricated simultaneously on one 4-inch wafer. The effect of fabrication issues on the resonant frequency of the device is also discussed. With a final chip size of about 1 cm2, a power output of 32.5 nW is successfully harvested with an external load of 17 MΩ, when a harmonic vibration source with an RMS acceleration amplitude of 0.03 g (∼0.3 m s−2) and a resonant frequency of 179 Hz is applied. These results can be improved in an optimized design. [ABSTRACT FROM AUTHOR]

Numerical simulations have been performed to analyze the influence of generation/recombination processes and leakage current through “interfacial” punctures on the results of electrical characterization of unipolar directly bonded semiconductor junctions by the methods previously proposed by the present author [Mater. Sci. Semicond. Process. 4 (2001) 177]. Physical quantities that characterize the electrical state of the bonded junction and phenomena brought about by the generation/recombination processes in the junction (static and high-frequency conduction due to minority carriers, influence of generation/recombination processes on the interfacial charge, etc.) are discussed. [Copyright &y& Elsevier]

Direct bonding at room temperature and ambient pressure is well established for planar surfaces (Tong and Gösele ) but numerous device elaborations require direct bonding of structured surfaces as for example for some MEMS or bio chips. Based on the one dimensional (1D) bonding wave model of Rieutord et al. (), a two dimensional (2D) simulation based on wafer mechanical deformation and trapped air flow will be presented. Our model takes into account possible lateral air flow, and is thus well suited to simulate, for example, the bonding of structured wafer with rectangular cavities whose length are parallel or perpendicular to the bonding wave direction. Experiments showed that rectangular cavities parallel to the direction of the bonding front propagation improve the bonding front velocity. A law of the evolution of the bonding wave speed depending on the width between the cavities has been obtained by studying the bonding of beams of varying width. [ABSTRACT FROM AUTHOR]

Hetero-integration of functional semiconductor layers and devices has received strong research interest from both academia and industry. While conventional techniques such as pick-and-place and wafer bonding can partially address this challenge, a variety of new layer transfer and chip-scale transfer technologies have been developed. In this review, we summarize such transfer techniques for heterogeneous integration of ultrathin semiconductor layers or chips to a receiving substrate for many applications, such as microdisplays and flexible electronics. We showed that a wide range of materials, devices, and systems with expanded functionalities and improved performance can be demonstrated by using these technologies. Finally, we give a detailed analysis of the advantages and disadvantages of these techniques, and discuss the future research directions of layer transfer and chip transfer techniques. [ABSTRACT FROM AUTHOR]

Wafer Bonding: Solution-Processed-ZnO-Mediated Semiconductor Bonding with High Mechanical Stability, Electrical Conductivity, Optical Transparency, and Roughness Tolerance (Adv. The ZnO-mediated bonds simultaneously exhibit high mechanical stability, electrical conductivity, optical transparency, and roughness tolerance. Devices, electronics, photonics, semiconductors, wafer bonding. [Extracted from the article]