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The controlled depletion of electrons in semiconductors is the basis for numerous devices. Reactive-ion etching provides an effective technique for fabricating both classical and quantum devices. However, Fermi-level pinning must be carefully considered in the development of small devices, such as quantum dots. Because of depletion, the electrical size of the device is reduced in comparison with its physical dimension. To investigate this issue in modulation-doped silicon single-electron transistors, we fabricate several types of devices in silicon-germanium heterostructures using two different etches, CF4 and SF6. We estimate the depletion width associated with each etch by two methods: (i) conductance measurements in etched wires of decreasing thickness (to determine the onset of depletion), and (ii) capacitance measurements of quantum dots (to estimate the size of the active region). We find that the SF6 etch causes a much smaller depletion width, making it more suitable for device fabrication. [ABSTRACT FROM AUTHOR]

Presents a study that examined the utility of Raman spectroscopy for the simultaneous determination of the composition and strain in thin germanium silicide layer semiconductors. Analysis of the composition dependence of Raman frequencies in bulk alloys; Evaluation of the strain shifts of the Raman frequencies; Determination of the composition and strain from Raman frequencies.

Presents a study which conducted a noise spectroscopy of semiconductor deep level centers in gallium arsenide-aluminum[sub x]gallium[sub 1-x]arsenide heterostructures. Description of the model; Experiment; Results and discussion.

Examines the properties of high-purity Al[subx]Ga[sub1-x]As grown by the metal-organic vapor-phase-epitaxy (MOVPE) technique using methyl precursors. Information on the growth and characterization of high-purity MOVPE semiconductor; Electrical properties of the semiconductor; Optical properties of semiconductor.

The spins of localized electrons in silicon are strong candidates for quantum information processing because of their extremely long coherence times and the integrability of Si within the present microelectronics infrastructure. This paper reviews a strategy for fabricating single electron spin qubits in gated quantum dots in Si/SiGe heterostructures. We discuss the pros and cons of using silicon, present recent advances, and outline challenges. PACS: 03.67.Pp, 03.67.Lx, 85.35.Be, 73.21.La [ABSTRACT FROM AUTHOR]

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as “bonded in-place”. We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained. [ABSTRACT FROM AUTHOR]

Direct evidence has been found, via hydrostatic pressure experiments, that the random distribution of Al and Ga atoms (alloy broadening) is the main cause of the nonexponential behavior of thermal emission processes from DX centers in Ga1-xAlxAs alloys (0.19≤x≤0.74). Isothermal single-shot emission transients at constant capacitance were used to measure the nonexponential behavior. Experimental values of the degree of nonexponentiality at ambient pressure, as a function of the Al content, are in good agreement with an alloy broadening model. When hydrostatic pressure up to 11 kbar is applied, the nonexponential behavior does not change, confirming its independence from variations in the conduction-band structure. [ABSTRACT FROM AUTHOR]

The article discusses the improved complementary metal oxide semiconductors (CMOS) performance via enhanced carrier mobility. According to the author, the amazing advancements achieved in Silicon CMOS have come primarily from scaling, i.e., from reducing the critical dimensions of the transistors. Since it is becoming increasingly difficult to further reduce critical dimensions such as the gate oxide thickness, alternative methods of improving transistor performance are being investigated. One approach is to increase the free carrier mobility in the active region of the device.

Si/Si[sub 1-x]Ge[sub x] heterostructures on improved silicon-on-sapphire substrates were grown epitaxially by ultrahigh vacuum chemical vapor deposition for application as p-channel field effect transistors. High-resolution triple-axis x-ray diffraction was used to analyze these structures quantitatively and to evaluate their thermal stability. Outdiffusion of Ge from the strained Si[sub 1-x]Ge[sub x] quantum well was observed after annealing at 850 °C. The amount of outdiffusion was comparable to that observed in Si[sub 1-x]Ge[sub x] structures on bulk Si wafers. © 1998 American Institute of Physics. [ABSTRACT FROM AUTHOR]