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This paper describes an approach for modeling the breakdown and snapback behavior of state-of-the-art MOSFET structures using equivalent-circuit description. Such models are required to enable circuit-level electrostatic discharge reliability simulations, which are a major challenge for the industry nowadays. Special attention is given to accurately describing the junction and gate leakage currents due to the increased tunneling generation in the scaled-down CMOS. Consistent parameter extraction procedures for the model parameters are described as well. [ABSTRACT FROM AUTHOR]

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating a gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable, Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages. [ABSTRACT FROM AUTHOR]