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We present a model for the tunneling field-effect transistor (TFET) comprising a series connection of a metal-oxide-semiconductor FET (MOSFET) with a gate-controllable tunneling diode. Through the introduction of MOSFET in the model, both operational regimes of TFET are handled correctly, with the tunneling diode dominating at low interband tunneling current and the MOSFET component dominating at high tunneling current. The comparison between our model, TCAD simulations and experimental data on TFETs with different gate oxide and channel thicknesses over the full range of gate and drain bias confirms the model's reliability and accuracy. At low tunneling current, the model further simplifies to a compact analytical model. With minor modifications, our model can also be applied to multi-gate TFET architectures. [ABSTRACT FROM AUTHOR]

The methodology of mobility extraction from the Y-function or from the transconductance peak is revisited in the context of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on a simple two-channel model, we discuss the biasing conditions that enable the Y-function to be applied to both single-gate (SG) and double-gate (DG) modes. Systematic mobility measurements in thick and ultrathin SOI transistors are presented for the front channel, back channel, and in quasi-double-gate mode. In SG-mode, the mobility is overestimated as soon as the opposite channel is activated. In partially depleted or relatively thick, fully depleted MOSFETs, the two channels are separated; hence, the total apparent mobility in DG mode is the sum of the front and back channel mobilities. By contrast, the two-channel model fails in ultrathin transistors, where the two channels become strongly coupled and volume inversion occurs. Volume inversion is reflected in a remarkable increase of the apparent mobility in DG mode. [ABSTRACT FROM AUTHOR]

The magnetoresistance technique has been introduced recently as a means of determining experimentally the mobility in bulk metal-oxide-semiconductor transistor and silicon-on-insulator devices. This technique does not require a precise determination of the channel length, and it also has the advantage of allowing mobility extraction when the application of other methods is problematic, notably with weak inversion and short device length. The magnetoresistance mobility extracted in this way is related but not identical to the normal effective drift mobility. In this work we simulate electron transport in the presence of a magnetic field for different device structures. The simulations allow us to study the conditions under which magnetoresistance mobility and effective mobility coincide, and to measure the difference, where it exists. We find that at low temperatures the two quantities coincide, while at room temperature a difference of more than 20% may appear. We take this to be a consequence of the energy difference between subbands and the resulting distribution of electrons among them. We then explain the fact that the two mobility measures coincide at low temperatures when only the ground subband is occupied by analyzing the energy dependence of the momentum relaxation time. [ABSTRACT FROM AUTHOR]

It has been reported previously [N. Bresson et al., Proceedings of the ECS Seventh International Symposium on Silicon-on-Insulator Technology and Devices, 2005 (unpublished), pp. 317–324; F Allibert et al., Proceedings of the IEEE International SOI Conference, Honolulu, HI, 2002 (unpublished)] that the film thickness strongly impacts the parameters extracted using the pseudo metal oxide semiconductor field effect transistor (pseudo-MOSFET) with the usual FET equations [S. Cristoloveanu and S. S. Li, Electrical Characterization of SOI Materials and Devices (Kluwer, Boston, MA, 1995)]. In this paper, we investigate the influence of top free-surface states on the pseudo-MOSFET characteristics by comparing passivated versus nonpassivated samples. The parameters of concern, investigated here, are carrier mobility, density of interface states, threshold (VT), and flatband (VFB) voltages. Based on systematic measurements and existing models [H. J. Hovel, Solid-State Electron. 47, 1311 (2003)] for VT, VFB, and subthreshold slope, we show how the free-surface impact increases as the film thickness is reduced. Comparison of extracted results with simulated curves demonstrates that, in state-of-the-art ultrathin silicon on insulator structures, the preparation and properties of the free surface are no longer negligible. [ABSTRACT FROM AUTHOR]

Presents a study which determined the non-homogeneous distribution of the carrier transport properties in silicon-on-insulator thin films synthesized by oxygen implantation. Use of gate-controlled p-type Hall devices; Determination of transport profiles based on metal oxide semiconductor (MOS) field effect; Channel resistance variation with gate voltage; Vertical profile of the MOS-hall device.

This paper investigates the total ionizing dose response of advanced nonplanar triple-gate transistors with short gate length, as a function of device geometry. Experiments and three-dimensional (3-D) simulations using a radiation dedicated code are used to analyze the buildup of a trapped charge in the buried oxide and its impact on the device electrical characteristics. The behaviors of three prospective nonplanar devices are detailed and compared to the total ionizing dose degradation of a planar fully depleted single-gate architecture. The Ω-gate FET is shown to be the most tolerant to a 500 krad(SiO2) total dose exposure thanks to the efficient control provided by the lateral gates over the electrostatic potential throughout the Si film and essentially at the Si fin/BOX interface. [ABSTRACT FROM AUTHOR]

Abstract: The inter-gate coupling effects in multiple-gate SOI devices with Omega configuration, metal gate and HfO2 dielectric are investigated. Electrical measurements together with 3D numerical simulations show that the back-gate influence is reduced for narrow devices due to a strong lateral coupling between the two lateral sides of the main gate. In spite of the full depletion of the transistor body, the threshold voltage and the subthreshold slope are no longer dependent on the back gate bias. It is also shown that the conduction channels can be separated in wide ΩFETs using the back-gate coupling in accumulation mode. DIVSB (drain-induced virtual substrate biasing) can be drastically reduced when the lateral coupling screens the drain influence. Narrow devices are then virtually immune to substrate effects. [Copyright &y& Elsevier]

Total ionizing dose effects are investigated for the first time in deca-nanometer fully depleted (FD) silicon-on-insulator (SOI) devices. Charge trapping and the influence of device architecture are investigated in transistors with and without external body contacts. A radiation-induced high current regime is measured in floating body devices, both at high and low drain voltages. The mechanism responsible for the onset of this high current regime is investigated by 2D numerical simulations, and shown to result from the combined effect of short gate length and floating body potential in the intrinsic Si film. Transistors with a doped Si film are less sensitive to the high current regime. The use of external body contact in the device architecture completely stops the onset of high current regime, whatever the device gate length. [ABSTRACT FROM AUTHOR]

Abstract: SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation in SOI MOSFETs can be improved dramatically by replacing the buried oxide with high thermal conductance insulators. The self-heating can be reduced by as much as 50–100°C. Yet, these materials feature high-K dielectric constant, which also affects the electrical properties: more severe short-channel effects, parasitic capacitances and drain-to-body fringing fields. The conciliation between the thermal and electrical properties of advanced SOI MOSFETs (50nm long, 10nm thick) is examined by comparing different SOI materials (air, SiO2, diamond, AlN, Al2O3, SiC) and MOS architectures. We demonstrate the advantage of a ground plane (GP) located under the buried insulator (BOX). Diamond is excellent candidate for relatively thick BOX whereas Al2O3 and SiC are suitable for ultra-thin BOX. These novel structures can be fabricated by wafer bonding technology. [Copyright &y& Elsevier]

Pseudo-metal-oxide-semiconductor (MOS) silicon-on-insulator (SOI) transistors are used to study the total ionizing, dose response of buried oxides. The concentrations of radiation-induced oxide-trap and interface-trap charge are separated using midgap and dual-transistor charge separation analysis techniques. Dual-transistor analysis is shown to be especially well suited for charge separation of pseudo-MOSFETs (Ψ-MOSFETs) because the electron conduction mode of this simple point-contact device resembles an pMOS transistor, and the hole conduction mode resembles a pMOS transistor. That this is a single device ensures that the dual-transistor assumption of equal oxide-trap charge in otherwise identical n and pMOS transistors is satisfied automatically. Both electron and hole conduction current-voltage (I-V) traces must extrapolate to a common, physically realistic midgap voltage; this is employed as a test for the self-consistency of Ψ-MOSFET data. Charge separation performed using midgap and dual-transistor analyses show good agreement for the devices employed in this paper. [ABSTRACT FROM AUTHOR]

This paper concerns recent results on photon emission used for hot carriers degradation analysis. In a first part. we focus on quantitative light emission analysis on is- and p- channel MOSFFLTs for bulk and SOI technologies. On each device, the photon counts for different gate and drain voltages were measured and compared with the value of the substrate current. This shows that the measured value of the substrate current in SOI devices can be inaccurate. In a second part, we investigate light emission spectra for some specific biases. These measurements allow a clear comparison of the different technologies. Finally, a photon emission technique was used to analyse hot carrier degradation in circuits, the highest emissions are observed on NMOS transistors working at high frequencies, but emission have also been detected on PMOS transistors. A clear correlation with the working frequencies of the MOS has also been demonstrated. [ABSTRACT FROM AUTHOR]

This paper revisits and adapts of the pseudo-MOSFET (Ψ-MOSFET) characterization technique for advanced fully depleted silicon on insulator (FDSOI) wafers. We review the current challenges for standard Ψ-MOSFET set-up on ultra-thin body (12 nm) over ultra-thin buried oxide (25 nm BOX) and propose a novel set-up enabling the technique on FDSOI structures. This novel configuration embeds 4 probes with large tip radius (100-200 μm) and low pressure to avoid oxide damage. Compared with previous 4-point probe measurements, we introduce a simplified and faster methodology together with an adapted Y-function. The models for parameters extraction are revisited and calibrated through systematic measurements of SOI wafers with variable film thickness. We propose an in-depth analysis of the FDSOI structure through comparison of experimental data, TCAD (Technology Computed Aided Design) simulations, and analytical modeling. TCAD simulations are used to unify previously reported thickness-dependent analytical models by analyzing the BOX/substrate potential and the electrical field in ultrathin films. Our updated analytical models are used to explain the results and to extract correct electrical parameters such as low-field electron and hole mobility, subthreshold slope, and film/BOX interface traps density. [ABSTRACT FROM AUTHOR]

Transport in double-gate (DG) transistors offers unusual properties due to the coupling between the two channels. We report on room-temperature negative transconductance in germanium-on-insulator DG transistors in the subthreshold regime. The effect is due to the coupling between conducting channels, analogous to the velocity modulation transistor (VMT). Unlike the VMT, our effect can be induced by either of the gates and arises not from a difference in the channel mobilities but from partial electric field screening at low channel densities combined with the density dependence of mobility. The negative transconductance becomes weaker as gate length LG is reduced. [ABSTRACT FROM AUTHOR]

In thin silicon-on-insulator structures, the gate effectively controls the longitudinal component of the electric field intensity in the pn+ junction, and thus the impact avalanche ionization of carriers. The present work proposes a device based on this operation principle: the control-impact-ionization-avalanche transistor, which achieves a transconductance of 0.14 (A/V)/mm. According to the developed theoretical model and preliminary experimental data, the device can be optimized to achieve very high transconductance and frequencies such as several (A/V)/mm at frequencies of the order of 100 MHz and lower, and about 1 (A/V)/mm in 0.1–1 THz range. [ABSTRACT FROM AUTHOR]

In short-channel silicon-on-insulator metal–oxide–semiconductor field-effect transistors, the condition for full depletion involves not only the body thickness and doping but also the channel length. The proximity of source and drain junctions reduces the apparent doping seen from the gate, which makes full depletion easier. Therefore, a transistor designed as partially depleted can behave as fully depleted. A simple analytical model for the length-doping transformation is proposed and validated by numerical simulations. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Abstract: A tunneling transistor (CONTUNT) compatible with ultra-thin SOI technology is presented. The gate controls the long depletion region of the drain p–n+ junction when the longitudinal component of the electric field becomes large enough to enable interband tunneling. The drain tunnel current strongly depends on the gate voltage. Our analytical model shows that the transistor transconductance and frequency of operation can reach about 1(A/V)/mm and 1THz, respectively. [Copyright &y& Elsevier]

We describe the operation of the novel SOI four-gate transistor (G4-FET) in the subthreshold region. The subthreshold slope, which may be defined with respect to either the junction gates or MOS gates, is adjustable using the remaining gates. A comparison of conventional MOSFET swings and G4-FET swings shows improved subthreshold slope. Systematic experimental data and simulations show the bias conditions for optimized performance. [Copyright &y& Elsevier]

Abstract: The mobility-thickness dependence in SOI films is clarified. Measurements in fully depleted SOI MOSFETs show that the low-field mobility at the front channel decreases by thinning the Si film or by sweeping the back gate from depletion into accumulation. We demonstrate that this mobility degradation is only apparent, being related to the potential value at the surface facing the channel. This opposite-surface potential induces an intrinsic vertical field which adds to the usual gate-related field. The mobility drop simply indicates a deviation from the low-field condition which cannot be achieved. We propose an updated model for proper extraction and interpretation of the low-field mobility. Pseudo-MOSFET results reveal the existence of a similar additional vertical field in bare SOI wafers, induced by charges present on the unpassivated surface. This intrinsic field increases in thinner films and affects pseudo-MOSFET conduction. The mobility decrease measured in SOI wafers with thinner films reflects the increasing impact of the intrinsic field and does not imply any degradation in quality of film-BOX interface. [Copyright &y& Elsevier]

Abstract: This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described. [Copyright &y& Elsevier]

Abstract: Ultra-thin Silicon-on-Insulator (SOI) transistor has proved to offer advantages over bulk MOSFETs for high-speed, low power applications. However, there is still a strong need to obtain an accurate understanding of carrier transport and mobility behaviour in these advanced devices. In this work, magnetoresistance technique is used to perform mobility measurements in Fully-Depleted Silicon-on-Insulator (FDSOI) MOSFETs. This technique has the advantage of allowing channel mobility measurement from weak to strong inversion without requiring the knowledge of the transistor’s effective channel length. The influence of different scattering mechanisms in the channel is investigated in details by obtaining mobility values at low temperatures. A new differential method enabling mobility extraction from pure channel magnetoresistance corrected for source–drain series resistance is presented. After the correction, in devices with large series resistance an increase in the extracted mobility is obtained in strong inversion, where the channel resistance is small and conventional mobility extraction is most affected by the impact of series resistance. [Copyright &y& Elsevier]

Abstract: A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-on-insulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si3N4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80nm down to 15nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices. [Copyright &y& Elsevier]

In this paper, the forward-biased gated-diode technique is proposed as a simple and reliable method for the determination of the recombination parameters in thin-film, fully depleted SOI MOS devices. Using modeling of gated-controlled volume and surface recombination components the behavior of the recombination current in a thin-film SOI gated-diode is analyzed. Measurement conditions simplifying the extraction of the recombination parameters and enabling discrimination between volume and surface contributions are described. The method has been applied to study recombination processes in the devices made on different SOI materials (UNIBOND, SIMOX, ZMR). [Copyright &y& Elsevier]