170 results on '"Wilson, Ron"'
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2. Teamwork makes challenging design task feasible
3. The next step in benchmarks
4. Speeds grow for configurable CPUs
5. IBM, Chartered pioneer 90-nm process compatibility -- With Samsung as licensee, fabs aim for design portability
6. Wireless USB radio weds programmable MCU
7. Chip pushes twisted-pair copper to 10 Gbits
8. Structured ASICs walk a fine line
9. Programmable fuse IP finds life after RFID role
10. Hard designs at 90 nm
11. Hope floats for new DRAM
12. Philips Semis pushes ARM outside MCU envelope -- 32-bit family adds fast I/O, analog I/O, more flash for board-level-like embedded
13. Tweaks to OS could change embedded design -- ADI ports Quadros Systems' RTXC to Blackfin processor, unifying APIs for DSP, RISC
14. Memory alternatives wait for flash to flame out -- But road map stretches for standby nonvolatile tech
15. Spansion moves NOR flash density into NAND territory -- Aggressive road map puts NOR on track to catch NAND in cost/bit by 2007
16. In a shift from venerable ASIC, OEMs now embrace ASSP -- Even more than cost issues, time-to-market spurs a move that is reshaping chip arena
17. For startup, power savings start in architecture -- Parameterized hardware blocks enforce designer's energy-efficiency scheme
18. Return of an intractable debate
19. Broadcom retasks SoC for Docsis v2.0 duties -- Chip can handle data, streaming media and voice for media gateway apps
20. Startup tips mask-configurable mixed-signal ASIC -- Triad to put analog blocks on base wafer with logic cells
21. Structured ASIC makes nest for CPU -- LSI Logic opens up a spot for cores on RapidChip
22. Two stretch configurable-CPU arena with new entries -- Faraday crafts 500-MHz ARM; Stretch rolls standard chip with SRAM-based array
23. Libraries, memory IP raised from the dead
24. Startup takes on memory/core-logic link -- SiliconPipe's tech moves 3.2 Gbits/s from controller to memory without a serdes
25. Delay- and phase-locked loops becoming reusable IP -- TrueCircuits and Agere separately tame these tough designs in DLL IP blocks
26. HD chips do double duty for standard definition -- Magis home media wireless chip set is repurposed for use in add-on equipment
27. Other half of low-power design
28. ARM, National team to manage SoC power hits -- PowerWise interface relies on dynamic voltage scaling and multiple-voltage islands
29. Darpa official provides a quantum reality check -- All the problems of analog computing seen cropping up
30. Intel tricks out 90-nm TCP/IP chip
31. Overview
32. Flash voltage: Less is more -- Low-cost controllers drive hunt for new ideas
33. Urgent call made for process tie-in -- Chip design, manufacturing must link up fast, say experts
34. Synthesis and the embedded CPU
35. Cut in energy draw for portables comes to life -- ARM, National Semi and Synopsys team on voltage-, clock-throttling approach
36. IP cores crowd SoCs -- Embedded processors utilize standard blocks
37. Teams scour RTL for design guidance -- ASIC makers use analysis tools to predict problem spots prior to synthesis
38. Leakage current leads 90-nm rogues' gallery
39. Reconfigurable computing arrays challenge DSPs -- A phalanx of programmable processors promises speedy dispatch of many algorithms
40. Are cell-based ASICs endangered?
41. Chip Express tips two series of structured ASICs -- Unlike competing products, CX5000 devices do not target FPGA conversion
42. Yields, packages hang up design below 100 nm
43. Another road to fast ASICs
44. Rx for looming analog angst
45. Micrel's Kendin group puts ARM-9, five-port switch together -- Integration brings CPU into analog design
46. SoC technical difficulties ahead; stand by
47. Even simple metal structures can pose huge hurdles, designers report -- Complex field-modeling problems tackled
48. German startup pushes analog CMOS higher
49. Algorithms ease route at 150 nm
50. Analysis techniques attack MEMS structure
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