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A new one-dimensional (1-D) nonlinear gate-source Cgs and gate-drain Cgd capacitance model designed for power-PHEMT transistors is presented. The capacitance values are extracted from measured [S] parameters, along a load-line corresponding to a power performance of an optimum amplifier design. The reliable resulting model predicts adequate power performances with small or large signals in reduced CPU time. This new model is validated by comparisons between load-pull power measurements at 25.5 GHz and harmonic balance simulations. It reveals good accuracy for AM/AM and AM/PM predictions. [ABSTRACT FROM PUBLISHER]

A nonlinear charge model for RF power FETs is presented. The model, intended for use in harmonic-balance simulators, calculates the time evolution of the nonlinear charge in a period of the steady-state regime. For that, the experimentally extracted capacitances are integrated using the device dynamic load cycle as integration path. The proposed approach is technology independent and it has been applied here to a Si LDMOSFET and a SiC MESFET. Load pull measurements have been performed to verify the validity of the model [ABSTRACT FROM PUBLISHER]

In this work we have determined a nonlinear electrothermal model for a low-noise GaAs MESFET, which enables evaluation of the time dependance of the internal temperature rise consecutive to a microwave overload impinging on the gate. This model takes into account the balance between the microwave energy loss under the gate in the active layer and energy conduction through the substrate during the pulse duration. We have conducted experimental determination of the critical peak power level for failure for several pulse durations and with the application of the model, we find that burnout is reached when the internal temperature exceeds 500°C. We are able to predict the vulnerability of a low-noise amplifier under microwave overload [ABSTRACT FROM PUBLISHER]