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Line resistance reduction in interconnects was achieved through Cu microstructure modulation. The modulation was performed via both raising annealing temperature and reducing the post-patterning dielectric aspect ratio and resulted in a bamboo-like Cu microstructure. Compared with the conventional polycrystalline, the modulated Cu microstructure also presents a lower resistivity increase rate with area scaling. A TaN stress control layer deposited on over-plated Cu surface was demonstrated to be critical for maintaining the Cu interconnect integrity after the high-temperature anneal. [ABSTRACT FROM AUTHOR]

Via resistance reduction in Cu interconnects was achieved through a pre-liner dielectric nitridation process prior to pure Ta liner deposition. Replacing TaN with Ta in the conventional liner stack reduces Cu via resistance, while the nitridation treatment maintains the interconnect integrity and reliability. Comprehensive evaluations including adhesion tests, parametric measurements, and electromigration evaluations of the pre-liner dielectric nitridation process were carried out to confirm the feasibility of reducing via resistance in advanced-node Cu/ultralow-k back-end-of-the-line interconnects. [ABSTRACT FROM PUBLISHER]

Modulation of Cu interconnect microstructure in a low- k dielectric was achieved at an elevated anneal temperature of 250 ^{\circ}{\rm C} . In contrast to the unpassivated conventional structure, a TaN metal passivation layer was deposited on the plated Cu overburden surface before annealing at the elevated temperature to prevent stress migration reliability degradation. As compared with the conventional structure annealed at 100 ^{\circ}{\rm C}$ , the elevated annealing process enabled further Cu grain growth, which then resulted in an increased Cu grain size and improved electromigration resistance in the interconnects. [ABSTRACT FROM AUTHOR]

Grain growth of Cu interconnects in a low-k dielectric was achieved at an elevated anneal temperature of 300 ^\circ\C without stress-migration-related reliability problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional anneal process at 100 ^\circ\C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects. [ABSTRACT FROM PUBLISHER]

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical vapor deposition. Both in situ and ex situ Co/SiC(N,H) capping processes were evaluated and have shown comparable parametrics to the control reference. For the ex situ capping process, the degree of electromigration (EM) resistance enhancement was observed to be dependent on the deposited Co thickness. Without increasing the Co cap thickness, further EM lifetime enhancement was observed from the in situ capping process. [ABSTRACT FROM AUTHOR]

As compared to conventional Cu reflows on Ta, lower temperature reflow anneals of Cu on Ru are achieved. Cu films are reflowed into 40-nm-wide features at an optimum temperature of 250 ^ \circ\C with a measured activation energy of 0.8 eV. Although higher anneal temperatures can shorten the process time, they also tend to increase hollow metal defects (missing Cu within patterned features). Compared to the control electroplated samples, the reflow-annealed samples do not show bigger Cu grains in the final structure. The observed resistance reduction from the reflowed samples is attributed to higher purity within the Cu interconnects. [ABSTRACT FROM AUTHOR]

Low-temperature reflow anneals of physical-vapor-deposited (PVD) Cu on Ru are achieved at a Cu/low- k integration-compatible low temperature of 250 ^\circ\C by surface diffusion. Feature-fill capability is also demonstrated in patterned features along with reasonable electrical measurements. As compared to typical impurity levels in the conventional electroplated Cu, the reflowed PVD Cu had higher purity, which then resulted in lower electrical resistance in the structures. Electromigration test results further confirmed the reliability of the reflowed-Cu/Ru interface. [ABSTRACT FROM AUTHOR]

Co films with various thicknesses were selectively deposited as Cu capping layers by chemical-vapor-deposition technique. Selectivity of the Co deposition between Cu and dielectric surfaces was improved by raising the deposition pressure. Degree of electromigration (EM) resistance enhancement was observed to be dependent on the deposited Co thickness. Compared to the no-Co control, significant EM lifetime enhancement was observed when the Co cap is thicker than 6 nm. [ABSTRACT FROM AUTHOR]

Cu films were directly deposited on Ru to check the feasibility of this process for Cu back-end-of-the-line integration beyond 32-nm technology nodes. Feature-fill enhancement was observed from the direct electroplating process as compared to the conventional one with the Cu electroplating performed on a PVD Cu seeding layer. Reasonable parametric yields were demonstrated for the direct electroplating process. The electromigration (EM) resistance of the directly plated Cu lines was degraded relative to that observed on the conventionally plated Cu lines. The observed EM resistance degradation is attributed to a weak interface between Ru/Cu, which can be caused by impurities from the electroplating process. [ABSTRACT FROM AUTHOR]