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The emergence of several technology options and the ever-broadening range of applications (e.g., automotive, smart grids, solar/wind farms) for power electronic devices suggest both a need and an opportunity to develop unifying principles to guide the development of wide bandgap (WBG) semiconductors. Unfortunately, power electronic devices are typically evaluated with a variety of elementary figure of merits (FOMs), which offer inconsistent/contradictory projections regarding the relative merits of emerging technologies. Indeed, one relies on the empirical (extrinsic) safe-operating area (SOA) of a packaged device to ultimately assess the performance potential of a technology option. Unfortunately, extrinsic SOA can only be calculated a posteriori, i.e., after precise measurement of the fabricated device parameters, making it suitable only for relatively mature technologies. Based on the insights of material-device-circuit-system performance analysis of a variety of idealized WBG power electronic devices (e.g., GaN HEMT, ${\beta }$ -Ga2O3 MOSFET), in this paper, we analytically derive a comprehensive, substrate-, self-heating-, and reliability-aware “intrinsic/limiting” safe operating area (SOA) that establishes a priori, i.e., before device fabrication, the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability. We establish the relevance of the intrinsic-SOA by comparing its prediction with a broad range of experimental data available in the literature. In between the traditional FOMs and extrinsic SOA, the intrinsic SOA allows fundamental/intuitive re-evaluation of intrinsic technology potential for power electronic devices and identifies specific performance bottlenecks and suggests strategies to circumvent them. [ABSTRACT FROM AUTHOR]

Traditional charge pumping (CP) technique relies on trap-assisted recombination from the source/drain to the body contact to characterize interface trap density (Nit) of classical bulk MOSFETs. A variant of the technique called single pulse CP (SPCP) allows interface trap characterization even if the bulk contact is absent, as in silicon-on-insulator (SOI) MOSFET. Unfortunately, neither technique is useful for devices with source-body-tied (SBT) and inhomogeneous channel doping profile, as in lateral diffused MOS (LDMOS) power transistors. Here, we propose a generalization of the CP/SPCP techniques, called Super SPCP (S2PCP), to extract position-resolved localized degradations (ΔNit) in an SBT LDMOS. Careful TCAD modeling and experimental characterizations demonstrate the effectiveness of the proposed approach. Our analysis provides deep insights into the physics of the SPCP technique, demonstrating that the approach can be used to characterize a variety of transistors with nontraditional doping profiles and contact configurations. [ABSTRACT FROM AUTHOR]

The uncertainties associated with technology‐specific and geography‐specific degradation rates make it difficult to calculate the levelized cost of energy, and thus the economic viability of solar energy. In this regard, millions of fielded photovoltaic modules may serve as a global testbed, where we can interpret the routinely collected time series maximum power point (MPP) data to assess the time‐dependent "health" of solar modules. The existing characterization methods, however, cannot effectively mine/decode these datasets to identify various degradation pathways. In this paper, we propose a new methodology called the Suns‐Vmp method, which offers a simple yet powerful approach to monitoring and diagnosing time‐dependent degradation of solar modules by using the MPP data. The algorithm reconstructs "IV" curves by using the natural illumination‐dependent and temperature‐dependent daily MPP characteristics as constraints to fit physics‐based circuit models. These synthetic IV characteristics are then used to determine the time‐dependent evolution of circuit parameters (eg, series resistance), which in turn allows one to deduce the dominant degradation modes (eg, solder bond failure) of solar modules. The proposed method has been applied to a test facility at the National Renewable Energy Laboratory. Our analysis indicates that the solar modules degraded at a rate of ~0.7%/year because of discoloration and weakened solder bonds. These conclusions are validated by independent outdoor IV measurements and on‐site imaging characterization. Integrated with physics‐based degradation models or machine learning algorithms, the method can also serve to predict the lifetime of photovoltaic systems. Inspired by the well‐known Suns‐Voc method, we have developed a novel technique called the Suns‐Vmp method that can interpret the routinely collected maximum power point (MPP) data of PV systems to produce insightful information regarding the underlying degradation mechanisms. The method can be applied to analyze solar modules installed across the globe to establish a comprehensive database of PV degradation. The resulting database will eventually facilitate geographic‐ and technology‐specific reliability‐aware design to improve module lifetime. [ABSTRACT FROM AUTHOR]

Spatially resolved precise prediction of local temperature T(\textit x,y,z) is essential to evaluate Arrhenius-activated interconnect (e.g., electromigration) and transistor reliability (e.g., NBTI, HCI, and TDDB). A 3-D finite-element modeling (FEM) do provide excellent results, but the calculation is too time-consuming for a structure that involves eight to ten layers of percolating interconnects, especially for fast turn-around reliability modeling. Here, an analytical model that can quickly/accurately determine \textit T(x,y,z) will reduce the design time of self-heated modern IC. In this paper, we 1) develop a physics-based electrothermal compact model for ICs to predict \textit T(x,y,z) based on the synthesis of effective medium theory, image charge theory, and Rent’s rule; 2) validate our model against 3-D FEM and experimental data; and 3) predict back-end-of-line (BEOL) reliability (i.e., electromigration at each layer) based on the temperature profile. Since our analytical model predicts changes in \textit T(x,y,z) with any given IC’s configuration (e.g., interconnect wire length and number distribution, metal volume fraction in BEOL, heat sinks mechanisms, materials, and type of devices), it suggests new opportunities for optimization of performance and reliability of modern ICs. [ABSTRACT FROM PUBLISHER]

Wearable and implantable electronic (WIE) devices are enabling a new generation of customized real-time health monitoring systems. Some of the highest performance systems involve MOSFET-based sensors as well as MOSFET-based digital and analog circuits. Protecting these transistors in a harsh fluidic environment is difficult because the requirement of wearability/flexibility demands ultrathin encapsulation. The charged ions (such as Na+) from body-fluids can diffuse rapidly through the thin encapsulation layer and destabilize the transistors, and render the component nonfunctional. In this paper, we develop an analytical framework and scaling theory for Na+ penetration into the encapsulation layer of WIE devices. Coupled with the physics of MOSFET degradation, the ion penetration model predicts lifetime of MOSFET-based electronics encapsulated by various types of encapsulating materials. The model is easily generalized to include multiple design parameters, such as stacks of encapsulation layers, encapsulation layer thicknesses, temperature/field dependent ion drift, and rate of dissolution of the encapsulation layer. Our simulations and experiments show that: 1) a multilayer encapsulation is essential to achieve multiobjective passivation, and 2) the encapsulation thickness must be optimized by accounting for charged ion penetration and dissolution of the encapsulation layer. [ABSTRACT FROM PUBLISHER]

While many groups attribute the greatly accelerated (i.e., excess) HCI degradation in modern transistors to the difference between the peak temperature and the average temperature ( \Delta T {L,{\rm{Diff}}}=\Delta T {L}^{\mathrm {pk}}-\Delta T{L}^{\mathrm {avg}}\mathbf {\gg 0} ) in self-heated FinFETs and other multigate transistors under dc or low-frequency stress, others find no evidence of the \Delta T {L,{\rm{Diff}}} -related excess degradation for ICs operating at high frequencies. In this letter, we resolve the puzzle by using a hierarchical electro-thermal device-circuit predictive model for HCI degradation to demonstrate that \Delta T {L,{\rm{Diff}}} {\to } {{0}} beyond a technology-specific transition frequency ( \omega {c} ), and therefore, excess HCI degradation disappears at \omega \gg \omega {c} . The proposed analytical model directly correlates HCI performance to power pulse trains characterized by frequency ( f ) and power duty cycle ( \boldsymbol\xi ) of a digital circuit. Self-heating will continue to reduce HCI-lifetime of surround gate transistors due to the increase of average temperature ( \Delta T {L}^{\mathrm {avg}} ), but the excess degradation caused by \Delta T {L,{\rm{Diff}}} will not be a concern for high-speed digital circuits. [ABSTRACT FROM AUTHOR]

Excellent electrostatic control offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes. Unfortunately, the GAA geometry is susceptible to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, \Delta T(x,y,z; t) , at the NW level is important for predicting activity-induced variability within an IC, as well as characterization of various reliability issues, such as, NBTI, PBTI, HCI, and TDDB that depend sensitively on self-heating. In this paper, a 3-D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in GAA devices. Our results identify complex heat dissipation pathways characterized by multiple time constants. First, the nanowires heat up quickly ( \tau _{\textrm {GAA-NW}}\sim \textrm {nSec} ), then heat spreads all over the gate contact pad ( \tau _{\textrm {G-pad}}\sim 100$ nSec), and finally, the heat exits through the heat sink at the bottom of the substrate ( \tau _{\textrm {sub}}\sim \textrm {mSec} ). A systematic thermoreflectance measurement of temperature helps us to identify the time constants, and validates the model. Our results have implications for the design, characterization, circuit-operation, and reliability of high-performance GAA devices. [ABSTRACT FROM AUTHOR]

Gate-all-around (GAA) MOSFETs use multiple nanowires (NWs) to achieve target I\mathrm{{\scriptscriptstyle ON}} , along with excellent 3-D electrostatic control of the channel. Although the self-heating effect has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatiotemporal resolution. In this paper, we develop an ultrafast high-resolution thermoreflectance (TR) imaging technique to: 1) directly observe the increase in local surface temperature of the GAA-FET with different number of NWs; 2) characterize/interpret the time constants of heating and cooling through high-resolution transient measurements; 3) identify critical paths for heat dissipation; and 4) detect in situ time-dependent breakdown of individual NW. Combined with the complementary approaches that probe the internal temperature of the NWs, the TR-images offer a high-resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for the validation of electrothermal models and the optimization of devices and circuits. In addition, we develop the simple compact model of the complex structure, which can explain experimental observations and can provide the internal temperature of the NWs. [ABSTRACT FROM AUTHOR]

One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative-bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent Vt degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based Vt model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: 1) static noise margin; 2) statistical READ and WRITE stability; 3) parametric yield; and 4) standby leakage current (IDDQ). We show that due to NBTI, READ stability of SRAM cell degrades, while WRITE stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation. [ABSTRACT FROM AUTHOR]

Actuation voltage shifts due to dielectric charging is a leading reliability concern in Radio-Frequency Micro-Electro-Mechanical Systems (RF-MEMS) capacitive switches. The inability to correlate dielectric surface roughness to charge accumulation makes predictive design difficult. We apply a sophisticated dielectric charging model on representative surfaces based on Atomic Force Microscopy (AFM) data, and show that there are significant, but predictable actuation voltage shifts due to surface roughness. The results suggest that surface roughness should be considered for accurate lifetime predictions, and simple metal-insulator-metal (MIM) capacitors may serve as a useful test structure for this phenomenon. [ABSTRACT FROM AUTHOR]