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10 results on '"Christine Rochange"'

1. Parallelizing industrial hard real-time applications for the parMERASA multicore

Author

Jörg Mische, Hugues Cassé, Florian Kluge, Sebastian Kehr, Sascha Uhrig, Francisco J. Cazorla, Armelle Bonenfant, Bert Böddeker, Lucie Matusova, Jaume Abella, Christian Bradatsch, Milos Panic, Zai Jian Jia Li, Mike Gerdes, Theo Ungerer, Carles Hernandez, Christine Rochange, Martin Frieb, Eduardo Quinones, David George, Zlatko Petrov, Ian Broster, Pavel Zaykov, Ralf Jahr, Hans Regler, Pascal Sainrat, Arthur Pyka, Haluk Ozaktas, Andreas Hugl, Alexander Stegmeier, Nick Lay, Mathias Rohde, Institute of Computer Science - University of Augsburg (ICS), Universität Augsburg [Augsburg], University of Augsburg [Augsburg], Honeywell Technology Solutions international development centre, Brno (HTS), Honeywell International S.r.o. [Prague], DENSO (JAPAN), Bauer Group (GERMANY), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Rapita Systems Ltd [York], Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Technische Universität Dortmund [Dortmund] (TU), project partners : Honeywell International s.r.o., Czech Republic, DENSO AUTOMOTIVE Deutschland GmbH,Germany, BAUER Maschinen GmbH, Germany, Rapita Systems Ltd, UK, Barcelona Supercomputing Center, Spain, Université Paul Sabatier, Toulouse, France, Technical University of Dortmund, Germany, and and University of Augsburg, Germany

Subjects
010302 applied physics, Multi-core processor, Control algorithm, business.industry, Computer science, Parallel design, Real-time computing, Automotive industry, Program transformation, 02 engineering and technology, Parallel computing, 01 natural sciences, 020202 computer hardware & architecture, Automatic parallelization, Hardware and Architecture, Embedded system, 0103 physical sciences, Management system, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Motion planning, business, Software
Abstract

International audience; The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on parallel design patterns that are timing analyzable. The parallelization approach was applied to parallelize the following industrial hard real-time programs: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH), and a diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH). This article focuses on the parallelization approach, experiences during parallelization with the applications, and quantitative results reached by simulation, by static WCET analysis with the OTAWA tool, and by measurement-based WCET analysis with the RapiTime tool.

Published
2016
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2. Effects of structured parallelism by parallel design patterns on embedded hard real-time systems

Author

Theo Ungerer, Pavel Zaykov, Ralf Jahr, Haluk Ozaktas, Mike Gerdes, Christine Rochange, University of Augsburg [Augsburg], Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Honeywell International S.r.o. [Prague]

Subjects
Pipelines, business.industry, Computer science, Data parallelism, Parallel design, Message systems, Real-time computing, Task parallelism, Static timing analysis, 02 engineering and technology, Parallel computing, Synchronization, Structured parallelism, 020202 computer hardware & architecture, Software, Parallel processing (DSP implementation), Synchronization (computer science), Parallel processing, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], 020201 artificial intelligence & image processing, business, Real-time systems
Abstract

International audience; Parallel multi-threaded applications are needed to gain advantage from multi- and many-core processors. Such processors are more frequently considered for embedded hard real-time with defined timing guarantees, too. The static timing analysis, which is one way to calculate the worst-case execution time (WCET) of parallel applications, is complex and time-consuming due to the difficulty to analyze the interferences of threads and the high annotation effort to resolve it.

Published
2014
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5. Estimation of Execution Time and Delays

Author

Pascal Raymond, Christine Rochange, Claire Maiza, VERIMAG (VERIMAG - IMAG), Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique de Grenoble (INPG)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Joseph Fourier - Grenoble 1 (UJF), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Chetto, Maryline

Subjects
Estimation, Computer science, Real-time computing, 0202 electrical engineering, electronic engineering, information engineering, Delay analysis, 020207 software engineering, [INFO]Computer Science [cs], 02 engineering and technology, Parallel computing, Execution time, 020202 computer hardware & architecture
Abstract

International audience; This chapter explains the usual methodology used to estimate worst case execution time (WCET) by static analysis. It analyzes three questions: (1) how to estimate delays due to interferences caused by another running program in multi-task systems; (2) how to analyze the execution time for more complex architectures in which the tasks share resources and therefore interfere with one another; and (3) what is the influence of the high-level design methods and their compilation on the WCET. The chapter presents the example of delays due to preemptions, and examines several approaches to compute the WCET of a task running on a multi-core architecture. The chapter lists some state-of-the-art tools dedicated to the WCET estimation. It also presents cache analysis techniques, and elements on the analysis of data caches and cache hierarchies. The analysis of the cache assigns a category to each instruction AlwaysHit, AlwaysMiss and NonClassified.

Published
2014
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6. parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Author

Arthur Pyka, Haluk Ozaktas, Dave George, João Carlos Lopes Fernandes, Hugues Cassé, Florian Kluge, Milos Panic, Pavel Zaykov, Theo Ungerer, Armelle Bonenfant, Ralf Jahr, Bert Böddeker, Zlatko Petrov, Hans Regler, Mike Gerdes, Andreas Hugl, Christian Bradatsch, Sascha Uhrig, Jaume Abella, Mathias Rohde, Sebastian Kehr, Francisco J. Cazorla, Ian Broster, Nick Lay, Christine Rochange, Pascal Sainrat, Eduardo Quinones, Jörg Mische, University of Augsburg [Augsburg], Honeywell International S.r.o. [Prague], DENSO (JAPAN), Bauer Group (GERMANY), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Rapita Systems Ltd [York], Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Universitat Politècnica de Catalunya [Barcelona] (UPC), Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), Technische Universität Dortmund [Dortmund] (TU), Barcelona Supercomputing Center – Centro Nacional de Supercomputación - BSC-CNS (SPAIN), Centre National de la Recherche Scientifique - CNRS (FRANCE), Consejo Superior de Investigaciones Científicas - CSIC (SPAIN), Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Universitat Politècnica de Catalunya - UPC (SPAIN), Honeywell (USA), Rapita System (USA), Technische Universität Dortmund - TU Dortmund (GERMANY), University of Augsburg (GERMANY), Institut de Recherche en Informatique de Toulouse - IRIT (Toulouse, France), Technical University of Catalonia – Barcelona Tech (Girona, Espagne), and Institut National Polytechnique de Toulouse - INPT (FRANCE)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Computer science, Embedded systems, Parallel programming, Real-time computing, Système d'exploitation, Automotive industry, Réseaux et télécommunications, 02 engineering and technology, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Many core, Architectures Matérielles, 0202 electrical engineering, electronic engineering, information engineering, Mixed criticality, Multi-core processor, Control algorithm, Multiprocessing systems, business.industry, Avionics, Systèmes embarqués, 020202 computer hardware & architecture, Embedded system, Scalability, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, 020201 artificial intelligence & image processing, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], business, System software
Abstract

International audience; Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

Published
2013
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7. Guest Editorial: Optimization of real-time systems

Author

Christine Rochange and James H. Anderson

Subjects
Control and Optimization, Computer Networks and Communications, Control and Systems Engineering, Computer science, Modeling and Simulation, Real-time computing, Electrical and Electronic Engineering, Computer Science Applications
Published
2014
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8. Merasa: Multicore execution of hard real-time applications supporting analyzability

Author

Francisco J. Cazorla, Christine Rochange, Pascal Sainrat, Stefan Metzlaff, Hugues Cassé, Michael Houston, Theo Ungerer, Mike Gerdes, Irakli Guliashvili, Sascha Uhrig, Guillem Bernat, Eduardo Quinones, Jörg Mische, Marco Paolieri, Zlatko Petrov, Julian Wolf, and Florian Kluge

Subjects
Multi-core processor, Computer science, business.industry, Real-time computing, 02 engineering and technology, Execution time, 020202 computer hardware & architecture, Instruction set, Software, Hardware and Architecture, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Electrical and Electronic Engineering, business, System software
Abstract

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor.

Published
2010
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9. RTOS support for parallel execution of hard real-time applications on the MERASA multi-core processor

Author

Mike Gerdes, Hugues Cassé, Sascha Uhrig, Julian Wolf, Florian Kluge, Theo Ungerer, Stefan Metzlaff, Jörg Mische, Pascal Sainrat, and Christine Rochange

Subjects
Multi-core processor, Computer science, business.industry, Real-time computing, 02 engineering and technology, Yarn, Thread (computing), computer.software_genre, Application software, Execution time, 020202 computer hardware & architecture, Low energy, Embedded system, visual_art, 0202 electrical engineering, electronic engineering, information engineering, visual_art.visual_art_medium, Operating system, 020201 artificial intelligence & image processing, business, computer, Real-time operating system, System software
Abstract

Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety-critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation or their interferences must be time-bounded. Thus, new requirements also arise for a real-time operating system (RTOS), in particular if the parallel execution of hard real-time applications should be supported. In this paper we focus on the MERASA system software as an RTOS developed on top of the MERASA multi-core processor. The MERASA system software fulfils the requirements for time-bounded execution of parallel hard real-time tasks. In particular we focus on thread control with synchronisation mechanisms, memory management and resource management requirements. Our evaluations show that all system software functions are time-bounded by a worst-case execution time (WCET) analysis.

Published
2010

10. A Case for Static Branch Prediction in Real-Time Systems

Author

C. Burguiere, Christine Rochange, and P. Sainrat

Subjects
Computer science, Real-time computing, Parallel computing, Hardware_CONTROLSTRUCTURESANDMICROPROGRAMMING, Aliasing (computing), Branch misprediction, Branch predictor, Compile time
Abstract

Taking dynamic branch prediction into account in WCET determination turns out to be complex, particularly because of the possible interferences between branches. In this paper we argue the case for using static instead of dynamic branch prediction: the aliasing problem is swept away and, in many cases, the estimated worst-case numbers of branch mispredictions are reduced. We propose a method to predict each branch at compile time. Experimental results show how effective this approach can be.

Published
2006
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