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Redundancy repair is a commonly used technique for memory yield improvement. In order to ensure high repair rate and final product yield, it is necessary to develop a repair scheme for the coming three-dimensional (3D) architecture of stacked DRAM. According to the JEDEC mobile memory technology roadmap, the interface of 3D DRAM, including the Wide I/O and High-Bandwidth Memory (HBM), is mainly classified as channel-based memories. In this paper, we propose a built-off self-test (BOSR) scheme at the controller level for channel-based 3D memory to enhance final product yield after the bonding of a memory cube to its corresponding logic die. The logic die contains the Channel controller, in which the BOSR circuit resides. Experimental results show that the repair rate is high with higher cluster failure ratio due to the flexible algorithm we choose. The area overhead is low and it decreases significantly when the memory size or channel count increases. The performance penalty is also low due to the parallel execution of address comparison and repair. Moreover, the manufacture cost is lower than conventional DRAM architecture due to allocator-based redundancies. Finally, the proposed scheme can easily be applied to other channel-based 3D memories. [ABSTRACT FROM AUTHOR]

Three-dimensional stacked memory stacking logic and memory dies are one of the most promising 3-D integration applications. This paper proposes two memory redundancy schemes to improve the yield of channelbased 3-D stacked DRAM by sharing spare memory across dies and satisfying channel constraints at the same time. The proposed schemes achieve much higher yield with very small area overhead than other memory redundancy schemes. [ABSTRACT FROM PUBLISHER]