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Single-event upsets are studied in digital logic cells in a radiation-hardened CMOS SOI technology. The sensitivity of SEU to different strike locations and hardening approaches is explored using broadbeam and focused beam experiments. Error distributions in chains of logic flip-flops are studied to determine the impact of various cell designs and hardening techniques on upset uniformity. [ABSTRACT FROM PUBLISHER]

We report heavy-ion microbeam and total dose data for a new complementary (npn + pnp) SiGe on thick-film SOI technology. Measured transient waveforms from heavy-ion strikes indicate a significantly shortened single-event-induced transient current, while maintaining the total dose robustness associated with SiGe devices. Heavy-ion broad-beam data confirm a reduced single event upset (SEU) cross-section in a high-speed shift register circuit. [ABSTRACT FROM AUTHOR]

We investigate the efficacy of mitigating radiation-based single event effects (SEE) within circuits incorporating SiGe heterojunction bipolar transistors (HBTs) built with an N-Ring, a transistor-level layout-based radiation hardened by design (RHBD) technique. Previous work of single-device ion-beam induced charge collection (IBICC) studies has demonstrated significant reductions in peak collector charge collection and sensitive area for charge collection; however, few circuit studies using this technique have been performed. Transient studies performed with Sandia National Laboratory's (SNL) 36 MeV ^16O microbeam on voltage references built with N-Ring SiGe HBTs have shown mixed results, with reductions in the number of large voltage disruptions in addition to new sensitive areas of low-level output voltage disturbances. Similar discrepancies between device-level IBICC results and circuit measurements are found for the case of digital shift registers implemented with N-Ring SiGe HBTs irradiated in a broadbeam environment at Texas A&M's Cyclotron Institute. The error cross-section curve of the N-Ring based register is found to be larger at larger ion LETs than the standard SiGe register, which is clearly counter-intuitive. We have worked to resolve the discrepancy between the measured circuit results and the device-level IBICC measurements, by re-measuring single-device N-Ring SiGe HBTs using a time-resolved ion beam induced charge (TRIBIC) set-up that allows direct capture of nodal transients. Coupling these measurements with full 3-D TCAD simulations provides complete insight into the origin of transient currents in an N-Ring SiGe HBT. The detailed structure of these transients and their bias dependencies are discussed, together with the ramifications for the design of space-borne analog and digital circuits using SiGe HBTs. [ABSTRACT FROM AUTHOR]

We report on the design and measured results of a new SiGe HBT radiation hardening by design technique called the “inverse-mode cascode” (IMC). A third-generation SiGe HBT IMC device was tested in a time resolved ion beam induced charge collection (TRIBICC) system, and was found to have over a 75% reduction in peak current transients with the use of an n-Tiedown on the IMC sub-collector node. Digital shift registers in a 1st-generation SiGe HBT technology were designed and measured under a heavy-ion beam, and shown to increase the LET threshold over standard npn only shift registers. Using the CREME96 tool, the expected orbital bit-errors/day were simulated to be approximately 70% lower with the IMC shift register. These measured results help demonstrate the efficacy of using the IMC device as a low-cost means for improving the SEE radiation hardness of SiGe HBT technology without increasing area or power. [ABSTRACT FROM AUTHOR]

Abstract-We investigate the single-event transient (SET) response of bandgap voltage references (BGRs) implemented in SiGe BiCMOS technology through heavy ion microbeam experiments. The SiGe BGR circuit is used to provide the input reference voltage to a voltage regulator. SiGe HBTs in the BGR circuit are struck with 36-MeV oxygen ions, and the subsequent transient responses are captured at the output of the regulator. Sensitive devices responsible for generating transients with large peak magnitudes (more than 5% of the dc output voltage) are identified. To determine the effectiveness of a transistor-layout-based radiation hardened by design (RHBD) technique with respect to immunity to SETs at the circuit level, the BGR circuit implemented with HETs surrounded by an alternate reverse-biased pn junction (n-ring RHBD) is also bombarded with oxygen ions, and subsequent SETs are captured. Experimental results indicate that the number of events causing transients with peak magnitude more than 5% above the dc level have been reduced in the RHBD version; however, with the inclusion of the n-ring RHBD, new locations for the occurrence of transients (albeit with smaller peak magnitude) are created. Transients at the transistor-level are also independently captured and are presented. It is demonstrated that while the transients are short at the transistor level (ns duration), relatively long transients are obtained at the circuit level (hundreds of nanoseconds). In addition, the impact of the SET response of the BGR on the performance of an ultra-high-speed 3-bit SiGe analog-to-digital converter (ADC) is investigated through simulation. It is shown that ion-induced transients in the reference voltage could eventually lead to data corruption at the output of the ADC. [ABSTRACT FROM AUTHOR]

We investigate transistor-level layout-based techniques for SEE mitigation in advanced SiGe HBTs. The approach is based on the inclusion of an alternate reverse-biased pn junction (n-ring) designed to shunt electron charge away from the sub-collector to substrate junction. The inclusion of the n-ring affects neither the dc nor ac performance of the SiGe HBT and does not compromise its inherent multi-Mrad TID tolerance. The effects of ion strike location and angle of incidence, as well as n-ring placement, area, and bias on charge collection are investigated experimentally using a 36 MeV O2 microbeam. The results indicate that charge shunting through the n-ring can result in up to a 90% reduction in collector collected charge for strikes outside the DT and a 18% reduction for strikes to the emitter center. 3-D transient strike simulations using NanoTCAD are used to verify the experimental observations, as well as shed insight into the underlying physical mechanisms. Circuit implications for this RHBD technique are discussed and recommendations made. [ABSTRACT FROM AUTHOR]