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Modular quantum computing architectures are a promising alternative to monolithic QPU (Quantum Processing Unit) designs for scaling up quantum devices. They refer to a set of interconnected QPUs or cores consisting of tightly coupled quantum bits that can communicate via quantum-coherent and classical links. In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. Therefore, mapping a quantum circuit onto a modular architecture involves finding an optimal assignment of logical qubits (qubits in the quantum circuit) to different cores with the aim to minimize the number of expensive inter-core operations while adhering to given hardware constraints. In this paper, we propose for the first time a Quadratic Unconstrained Binary Optimization (QUBO) technique to encode the problem and the solution for both qubit allocation and inter-core communication costs in binary decision variables. To this end, the quantum circuit is split into slices, and qubit assignment is formulated as a graph partitioning problem for each circuit slice. The costly inter-core communication is reduced by penalizing inter-core qubit communications. The final solution is obtained by minimizing the overall cost across all circuit slices. To evaluate the effectiveness of our approach, we conduct a detailed analysis using a representative set of benchmarks having a high number of qubits on two different multi-core architectures. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits that require on average 0.78 inter-core communications per two-qubit gate., Submitted to IEEE QCE 2023

Holographic quantum-error correcting codes are models of bulk/boundary dualities such as the anti-de Sitter/conformal field theory (AdS/CFT) correspondence, where a higher-dimensional bulk geometry is associated with the code's logical degrees of freedom. Previous discrete holographic codes based on tensor networks have reproduced the general code properties expected from continuum AdS/CFT, such as complementary recovery. However, the boundary states of such tensor networks typically do not exhibit the expected correlation functions of CFT boundary states. In this work, we show that a new class of exact holographic codes, extending the previously proposed hyperinvariant tensor networks into quantum codes, produce the correct boundary correlation functions. This approach yields a dictionary between logical states in the bulk and the critical renormalization group flow of boundary states. Furthermore, these codes exhibit a state-dependent breakdown of complementary recovery as expected from AdS/CFT under small quantum gravity corrections., 9 pages; comments are welcome

We introduce a novel approach to translate arbitrary 3-SAT instances to Quadratic Unconstrained Binary Optimization (QUBO) as they are used by quantum annealing (QA) or the quantum approximate optimization algorithm (QAOA). Our approach requires fewer couplings and fewer physical qubits than the current state-of-the-art, which results in higher solution quality. We verified the practical applicability of the approach by testing it on a D-Wave quantum annealer.

In most qubit realizations, prototype devices are available and are already utilized in both industry and academic research. Despite being severely constrained, hardware- and algorithm-aware quantum circuit mapping techniques have been developed for enabling successful algorithm executions during the NISQ era, targeting mostly technologies with high qubit counts. Not so much attention has been paid to the implementation of compilation methods for quantum processors based on spin-qubits due to the scarce availability of current experimental devices and their small sizes. However, based on their high scalability potential and their rapid progress it is timely to start exploring quantum circuit mapping solutions for these spin-qubit devices. In this work, we discuss the unique mapping challenges of a scalable spin-qubit crossbar architecture with shared control [arXiv:1711.03807] and introduce $\textit{SpinQ}$, the first native compilation framework for scalable spin-qubit architectures that maps quantum algorithms on this crossbar architecture. At the core of $\textit{SpinQ}$ is the $\textit{Integrated Strategy}$ that addresses the unique operational constraints of the crossbar while considering compilation (execution time) scalability, having a $O(n)$ computational complexity. To evaluate the performance of $\textit{SpinQ}$ on this novel architecture, we compiled a broad set of well-defined quantum circuits and performed an in-depth analysis based on multiple metrics such as gate overhead, depth overhead, and estimated success probability, which in turn allowed us to create unique mapping and architectural insights. Finally, we propose novel mapping technique improvements for the crossbar architecture that could increase algorithm success rates and potentially inspire further research on quantum circuit mapping techniques for other scalable spin-qubit architectures., 18 pages, 16 figures

Current monolithic quantum computer architectures have limited scalability. One promising approach for scaling them up is to use a modular or multi-core architecture, in which different quantum processors (cores) are connected via quantum and classical links. This new architectural design poses new challenges such as the expensive inter-core communication. To reduce these movements when executing a quantum algorithm, an efficient mapping technique is required. In this paper, a detailed critical discussion of the quantum circuit mapping problem for multi-core quantum computing architectures is provided. In addition, we further explore the performance of a mapping method, which is formulated as a partitioning over time graph problem, by performing an architectural scalability analysis.

Many promising applications of quantum computing with a provable speedup center around the HHL algorithm. Due to restrictions on the hardware and its significant demand on qubits and gates in known implementations, its execution is prohibitive on near-term quantum computers. Aiming to facilitate such NISQ-implementations, we propose a novel circuit approximation technique that enhances the arithmetic subroutines in the HHL, which resemble a particularly resource-demanding component in small-scale settings. For this, we provide a description of the algorithmic implementation of space-efficient rotations of polynomial functions that do not demand explicit arithmetic calculations inside the quantum circuit. We show how these types of circuits can be reduced in depth by providing a simple and powerful approximation technique. Moreover, we provide an algorithm that converts lookup-tables for arbitrary function rotations into a structure that allows an application of the approximation technique. This allows implementing approximate rotation circuits for many polynomial and non-polynomial functions. Experimental results obtained for realistic early-application dimensions show significant improvements compared to the state-of-the-art, yielding small circuits while achieving good approximations.

Flag-style fault-tolerance has become a linchpin in the realization of small fault-tolerant quantum-error correction experiments. The flag protocol's utility hinges on low qubit overhead, which is typically much smaller than in other approaches. However, as in most fault-tolerance protocols, the advantages of flag-style error correction come with a tradeoff: fault tolerance can be guaranteed, but such protocols involve high-depth circuits, due to the need for repeated stabilizer measurements. Here, we demonstrate that a dynamic choice of stabilizer measurements, based on past syndromes, and the utilization of elements from the full stabilizer group, leads to flag protocols with lower-depth syndrome-extraction circuits for the [[5,1,3]] code, as well as for the Steane code when compared to the standard methods in flag fault tolerance. We methodically prove that our new protocols yield fault-tolerant lookup tables, and demonstrate them with a pseudothreshold simulation, showcasing large improvements for all protocols when compared to previously-established methods. This work opens the dialogue on exploiting the properties of the full stabilizer group for reducing circuit overhead in fault-tolerant quantum-error correction., Comment: submitted to IEEE International Conference on Quantum Computing and Engineering (QCE23)

To solve 3SAT instances on quantum annealers they need to be transformed to an instance of Quadratic Unconstrained Binary Optimization (QUBO). When there are multiple transformations available, the question arises whether different transformations lead to differences in the obtained solution quality. Thus, in this paper we conduct an empirical benchmark study, in which we compare four structurally different QUBO transformations for the 3SAT problem with regards to the solution quality on D-Wave's Advantage_system4.1. We show that the choice of QUBO transformation can significantly impact the number of correct solutions the quantum annealer returns. Furthermore, we show that the size of a QUBO instance (i.e., the dimension of the QUBO matrix) is not a sufficient predictor for solution quality, as larger QUBO instances may produce better results than smaller QUBO instances for the same problem. We also empirically show that the number of different quadratic values of a QUBO instance, combined with their range, can significantly impact the solution quality.

3SAT instances need to be transformed into instances of Quadratic Unconstrained Binary Optimization (QUBO) to be solved on a quantum annealer. Although it has been shown that the choice of the 3SAT-to-QUBO transformation can impact the solution quality of quantum annealing significantly, currently only a few 3SAT-to-QUBO transformations are known. Additionally, all of the known 3SAT-to-QUBO transformations were created manually (and not procedurally) by an expert using reasoning, which is a rather slow and limiting process. In this paper, we will introduce the name Pattern QUBO for a concept that has been used implicitly in the construction of 3SAT-to-QUBO transformations before. We will provide an in-depth explanation for the idea behind Pattern QUBOs and show its importance by proposing an algorithmic method that uses Pattern QUBOs to create new 3SAT-to-QUBO transformations automatically. As an additional application of Pattern QUBOs and our proposed algorithmic method, we introduce approximate 3SAT-to-QUBO transformations. These transformations sacrifice optimality but use significantly fewer variables (and thus physical qubits on quantum hardware) than non-approximate 3SAT-to-QUBO transformations. We will show that approximate 3SAT-to-QUBO transformations can nevertheless be very effective in some cases.

We have implemented a gated-based quantum version of a restricted Boltzmann machine for approximating the ground state of a Pauli-decomposed qubit Hamiltonian. During the implementation and evaluation, we have noticed a variety of unexpected topics. It starts from limitations due to the structure of the algorithm itself and continues with constraints induced by specific quantum software development kits, which did not (yet) support necessary features for an efficient implementation. In this paper we systematically summarize our findings and categorize them according to their relevance for the implementation of similar quantum algorithms. We also discuss the feasibility of executing such implementations on current NISQ devices., Comment: 6 pages

Quantum circuits are widely used for benchmarking quantum computers and therefore crucial for the development and improvement of full-stack quantum computing systems. To execute such circuits on a given quantum processor, they have to be modified to comply with its physical constraints. That process is done during the compilation phase and known as mapping of quantum circuits. The result of the mapping procedure is highly dependent not only on the hardware constraints, but also on the properties of the circuit itself. In this paper, we propose to explore the structure of quantum circuits to get detailed insights into their success rate when being executed on a given quantum device while using a specific compilation technique. To this purpose, we have characterized a large body of quantum circuits by extracting graph theory-based properties from their corresponding qubit interaction graphs and afterwards clustered them based on those and other commonly used circuit-describing parameters. This characterization will help i) to perform an in-depth analysis of quantum circuits and their structure and group them based on similarities; ii) to better understand and compare the mapping performance when run on a quantum processor and, later on, iii) to develop mapping techniques that use information from both, algorithms and quantum devices. Our simulation results show a clear correlation between interaction graph-based parameters as well as clusters of circuits with their mapping performance metrics when considering the constraints of a Surface-97 processor, as well as of IBM-53 Rochester and Aspen-16 devices. In addition to that, we provide an up-to-date collection of quantum circuits and algorithms taken from well-known sources with the goal of having an all-gathering, easy-to-use, categorized and characterized benchmark set available for the quantum computing community.

We report the Atos Q-score for D-Wave's quantum devices, classical algorithms and hybrid quantum-classical solver. Computing the Q-score entails solving the Max-Cut problem for increasingly large graphs. This work presents the first computation of the Q-score on a quantum device and shows how these quantum devices compare to classical devices at solving optimisation problems. We use D-Wave's standard methods out of the box with a time limit of 60 seconds. The Q-score for D-Wave's 2000Q and Advantage devices are 70 and 140, respectively. The Q-score for two of D-Wave's classical algorithms, based on tabu search and simulated annealing respectively, are 2,300 and 5,800. Finally, we report the out-of-the-box hybrid approach to have a Q-score of 12,500., Comment: 8 pages, 6 figures. Submitted to IEEE QSW 2022

The analysis of network structure is essential to many scientific areas, ranging from biology to sociology. As the computational task of clustering these networks into partitions, i.e., solving the community detection problem, is generally NP-hard, heuristic solutions are indispensable. The exploration of expedient heuristics has led to the development of particularly promising approaches in the emerging technology of quantum computing. Motivated by the substantial hardware demands for all established quantum community detection approaches, we introduce a novel QUBO based approach that only needs number-of-nodes many qubits and is represented by a QUBO-matrix as sparse as the input graph's adjacency matrix. The substantial improvement on the sparsity of the QUBO-matrix, which is typically very dense in related work, is achieved through the novel concept of separation-nodes. Instead of assigning every node to a community directly, this approach relies on the identification of a separation-node set, which -- upon its removal from the graph -- yields a set of connected components, representing the core components of the communities. Employing a greedy heuristic to assign the nodes from the separation-node sets to the identified community cores, subsequent experimental results yield a proof of concept. This work hence displays a promising approach to NISQ ready quantum community detection, catalyzing the application of quantum computers for the network structure analysis of large scale, real world problem instances.

Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is crucial to develop tools that allow specific design space explorations. To this aim, in this paper we present a technique to perform a spatio-temporal characterization of quantum circuits running in multi-chip quantum computers. Specifically, we focus on the analysis of the qubit traffic resulting from operations that involve qubits residing in different cores, and hence quantum communication across chips, while also giving importance to the amount of intra-core operations that occur in between those communications. Using specific multi-core performance metrics and a complete set of benchmarks, our analysis showcases the opportunities that the proposed approach may provide to guide the design of multi-core quantum computers and their interconnects., Comment: 7 pages, to be presented at the ACM NanoCom 2022

The efficiency of Quantum Characterisation, Verification, and Validation (QCVV) protocols highly hinges on the agreement between the assumed noise model and the underlying error mechanisms. As a matter of fact, errors in Quantum Processing Units (QPUs) incorporate various aspects of context-dependability which are overlooked by the majority of the commonly used QCVV protocols. As QCVV protocols are indispensable when it comes to characterizing and evaluating quantum operations, there is a serious need for a detailed characterization taking into account such aspects. In this work, we address these shortcomings by designing a context-aware version of the gate set tomography (GST) protocol. Our experiment selection approach is based on a polynomial quantification of the accumulation of errors within the designed circuits. Using simulated QPUs, we show that this technique enables a characterization with an inaccuracy reaching $10^{-5}$. Furthermore, we use our proposed protocol to experimentally infer context-dependent errors, namely crosstalk and memory effects, in a publicly accessible cloud-based superconducting qubits platform. Our results show that when the GST is upgraded to include such features of context-awareness, a large coherence in the errors is observed. These findings open up possibilities of drastically reducing the errors within the currently demonstrated QPUs.

When solving propositional logic satisfiability (specifically 3SAT) using quantum annealing, we analyze the effect the difficulty of different instances of the problem has on the quality of the answer returned by the quantum annealer. A high-quality response from the annealer in this case is defined by a high percentage of correct solutions among the returned answers. We show that the phase transition regarding the computational complexity of the problem, which is well-known to occur for 3SAT on classical machines (where it causes a detrimental increase in runtime), persists in some form (but possibly to a lesser extent) for quantum annealing., 13 pages, published at QTOP 2019