Search

The diode-front-end (DFE) cascaded H-bridge (CHB) inverter has prevailed in the nonregenerative industry drive domain for high power medium voltage applications due to its modularity, scalability, and fault-tolerant capability. The regenerative version of the CHB drives is made possible by adding the extra active-front-end (AFE) rectifier in each power cell, such as a three-phase Pulse width modulation (PWM) rectifier. However, AFE introduces the switching harmonics which requires to be attenuated by designing a grid interfaced filter to comply with the harmonic standard IEEE 519-2014. High-order filters like LCL filters are not preferred due to complex inherent resonances in a multiparallel AFE system. A large number of capacitive components in the system rouse multiple resonances, which decreases system reliability and modularity. This article proposes an active filtering strategy based on the optimal asymmetric carrier-shifting method for regenerative CHB drives with only L filters. The required filter size is reduced significantly while complying with IEEE 519-2014 standard and thus improves the overall size, cost, and efficiency. The proposed filtering strategy is validated experimentally using a seven-level regenerative CHB drive. [ABSTRACT FROM AUTHOR]

This article proposes a new fault-tolerant technique to increase the maximum balanced line-to-line output voltage of the cascaded H-bridge (CHB) motor drives. The CHB converters have been widely used for medium-voltage motor drives due to their scalability and reliability features. A significant indicator of the reliability is the maximum balanced line-to-line voltage amplitude under fault conditions. This article adopts a nonsymmetrical selective harmonic elimination (SHE) formulation to further extend the output voltage range with a good harmonic profile under fault conditions. The dc current component can be regulated for the dynamic braking operation. Based on the nonsymmetrical SHE formulation, the fault-tolerant problem that achieves the maximum output voltage range and good harmonic profile is converted to an optimization problem, which can be solved by the proposed optimization framework. By properly selecting the output voltage waveforms, the entire converter voltage capability can be achieved under fault conditions with a good harmonic profile. The performance of the proposed method is evaluated experimentally on a seven-level CHB motor drive. [ABSTRACT FROM AUTHOR]

The series connection of low-power modules is an alternative solution to realize a multilevel inverter. Unlike a cascade connection, the series connection approach significantly reduces the number of isolated dc sources, thereby the design complexity, cabling of the transformer, and overall system cost become low. In this article, the operation of the series-connected multilevel inverter is presented for a five-level operation, and it is realized by using two three-level half-bridge diode clamp converter modules per phase. Hence, each phase of the series-connected multilevel inverter requires a single isolated dc source. In the series-connected multilevel inverter, the net dc-bus voltage will be equally distributed between four dc-bus capacitors. Therefore, the converter generates a multilevel voltage waveform with uniform steps and ensures equal voltage stress on the semiconductor devices. To achieve these objectives, a space vector pulsewidth modulation scheme with an additional voltage balancing approach is employed. The feasibility of series-connected multilevel inverter is validated through simulations and a scaled-down laboratory prototype under steady-state and transient conditions. [ABSTRACT FROM AUTHOR]

In this article, a new five-level voltage source inverter is proposed for high-power applications. The proposed inverter is competitive in performance, component count, and control complexity compared with the conventional multilevel inverters. Also, the proposed inverter has a simple structure as it does not have any dc-link neutral points, unlike hybrid converters. Furthermore, the proposed topology can be connected in a back-to-back due to the presence of a common dc-link. Also, there is no need of isolated dc source and a complex phase-shifting transformer. In addition, a simple voltage balancing approach based on a level-shifted carrier pulsewidth modulation scheme is proposed to control the flying capacitor voltages. The proposed approach will make use of the redundancy switching states to balance the flying capacitor voltages in the proposed inverter. The steady-state and transient performance of the proposed five-level voltage source inverter and voltage balancing approach is validated through MATLAB simulation studies at different power factors and modulation indices. The simulation studies are further evaluated experimentally by a scaled-down laboratory prototype. Furthermore, the feasibility of the proposed topology is analyzed under the performance indices of voltage and current harmonic distortion, flying capacitor voltage ripples, converter power losses, and converter efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]

In this letter, a new control method based on the sinusoidal pulsewidth modulation scheme is proposed to control capacitor voltages of a T-type four-level nested neutral-point-clamped (NNPC) inverter. The T-type four-level NNPC inverter has a lower number of switches and components compared with other four-level classic and advanced inverters, which make this topology attractive for high-power medium-voltage applications. This topology has been proposed and studied with the assumption of constant dc sources instead of flying capacitors. In this letter, a simple single-phase modulator is developed to balance flying capacitor voltages. The performance and the feasibility of the proposed control technique are evaluated experimentally under a steady-state and transient conditions and for different modulation indexes and loads. The experimental results demonstrate the effectiveness of the developed control method to control the capacitors’ voltages. [ABSTRACT FROM AUTHOR]

The five-level modular neutral-point-clamped (5L-MNPC) converter is realized by connecting two three-level neutral-point-clamped modules in series. For five-level operation, each dc-bus capacitor voltage of the modular neutral-point-clamped topology should be regulated at one-fourth of the net dc-bus voltage. In this letter, a simple voltage-balancing approach based on the carrier-based modulation scheme is proposed to achieve the above objectives. The proposed approach uses the redundancy switching states along with the current direction and the instantaneous value of the dc-bus capacitor voltage to achieve the voltage balancing in the 5L-MNPC topology. The dynamic performance of the 5L-MNPC topology with the proposed voltage-balancing approach is verified experimentally. [ABSTRACT FROM AUTHOR]

Compared with multilevel space vector modulation, level-shifted multicarrier sinusoidal pulsewidth modulation (SPWM) for nested neutral point-clamped (NNPC) inverters requires much less calculations and implementation efforts, but the existing conventional SPWM cannot suppress the severe flying-capacitor (FC) voltage ripples under low output-frequency conditions. In order to solve this problem, a multicarrier-based PWM strategy with complete voltage balance control (VBC) capacity is proposed in this paper. For NNPC inverters operating under low output-frequency conditions, two preprocessing steps, the zero-sequence injection and the modulation-signal rearrangement, are proposed before the comparisons between level-shifted carriers and modulating signals. These preprocessing steps make the average currents flowing through FCs zero, which is beneficial to greatly reduce the FC voltage ripples under low output-frequency conditions. Together with additional VBC, the proposed modulation can assure the FC voltages balanced under the entire output-frequency conditions. Principles and implementation processes of proposed modulation techniques and VBC methodsare elaborated in detail and compared with conventional modulation methods. Both simulation results from a 5-MVA system and experimental results based on a 5-kVA platform are presented to verify the effectiveness. [ABSTRACT FROM AUTHOR]

Four-level nested neutral-point clamped (NNPC) inverters experience severe voltage balancing problems under low output-frequency conditions when the conventional four-level space vector modulation (4L-SVM) technique is applied, which limits their wider application. In order to get a complete control of the flying-capacitor voltages, and to alleviate the calculation burden of conventional 4L-SVM, a simplified but effective 4L-SVM technique along with the voltage balance control (VBC) function is proposed in this paper. For low modulation indexes, zero and small vectors are selectively utilized and distributed to force the average charging and discharging time of flying capacitors to be equal to each other during every switching period, so that voltage ripples are greatly reduced to be within an acceptable level under low output-frequency conditions. For high modulation indexes, the simplification of conventional 4L-SVM for NNPC inverters into two-level SVM is proposed to reduce the computation complexity. Principles of the proposed 4L-SVM and VBC are elaborated in detail. The steady-state, transient-state, and VBC performances are investigated and compared with the case where the conventional 4L-SVM is applied. Simulation results of a 5 MVA inverter system and experimental results of a scaled-down 5 kVA inverter system are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a new five-level voltage source inverter for medium-voltage high-power applications. The proposed inverter is based on the upgrade of a four-level nested neutral-point clamped converter. This inverter can operate over a wide range of voltages without the need for connecting power semiconductor in series, has high-quality output voltage and fewer components compared to other classic five-level topologies. The features and operation of the proposed converter are studied and a simple sinusoidal PWM scheme is developed to control and balance the flying capacitors to their desired values. The performance of the proposed converter is evaluated by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype. [ABSTRACT FROM AUTHOR]

Pulse-width modulated (PWM) full-bridge boost converters are used in applications where the output voltage is considerably higher than the input voltage. Zero-voltage-switching (ZVS) is typically implemented in these converters. A new ZVS-PWM full-bridge converter is proposed in this paper. The proposed converter does not have any of the disadvantages associated with other converters of this type, including a complicated auxiliary circuit, increased current stresses in the main power switches, and load-dependent ZVS operation. The operation of the proposed converter, its steady-state characteristics, and its design are explained and examined. The feasibility of the converter is confirmed with results obtained from an experimental prototype. [ABSTRACT FROM AUTHOR]

A new three-level ac–dc single-stage converter that can operate with standard phase-shift pulsewidth modulation is proposed in this letter. In this letter, the operation of the converter is explained, and its feasibility is confirmed with experimental results obtained from a prototype converter. Finally, the efficiency of the new converter is compared with that of a previously proposed converter of the same type, and it is shown that the new converter has better efficiency, particularly for light-load operation. [ABSTRACT FROM PUBLISHER]