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Single-event upsets are observed in a 72-layer 3-D NAND flash memory operated in a single-level cell mode after low-energy proton (500 keV–1.2 MeV) and heavy-ion irradiation. The layer-by-layer error count is analyzed to visualize the stopping of low-energy protons within the memory stack, and Monte Carlo simulations are correlated with the experimental data. Direct ionization by low-energy protons is identified by 3-D data analysis and the energy dependence of device-sensitive cross section. Heavy-ion data is also presented for comparison. [ABSTRACT FROM AUTHOR]

We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previous partially depleted technology generations (32 and 45 nm). The per-bit cross section is approximately an order of magnitude lower than the previous generations with a higher onset linear energy transfer (LET). No dependence on roll angle or input pattern was found. Tilt angle data follow the cosine law. Increasing the SRAM array supply voltage from the minimum tested 0.73 V to the maximum 1.08 V decreases SEE sensitivity by as much as 8%. Decreasing the p-well voltage from the nominal 0 V to the maximum −2 V increases the SEE cross section by as much as 2 ×. The n-well voltage has little effect on the SEE sensitivity due to the specifics of the transistor layout in the SRAM. Changing both the n- and p-well voltages simultaneously results in identical results as when only the p-well voltage was changed. [ABSTRACT FROM AUTHOR]

We report low-energy proton and low-energy alpha particle SEE data on a 32 nm SOI CMOS SRAM that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 MeV. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment. [ABSTRACT FROM PUBLISHER]

The potential for using the degraded beam of high-energy proton radiation sources for proton hardness assurance testing for ICs that are sensitive to proton direct ionization effects are explored. SRAMs were irradiated using high energy proton radiation sources (\sim 67-70~MeV). The proton energy was degraded using plastic or Al degraders. Peaks in the SEU cross section due to direct ionization were observed. To best observe proton direct ionization effects, one needs to maximize the number of protons in the energy spectrum below the proton energy SEU threshold. SRIM simulations show that there is a tradeoff between increasing the fraction of protons in the energy spectrum with low energies by decreasing the peak energy and the reduction in the total number of protons as protons are stopped in the device as the proton energy is decreased. Two possible methods for increasing the number of low energy protons is to decrease the primary proton energy to reduce the amount of energy straggle and to place the degrader close to the DUT to minimize angular dispersion. These results suggest that high-energy proton radiation sources may be useful for identifying devices sensitive to proton direct ionization. [ABSTRACT FROM AUTHOR]

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts. [ABSTRACT FROM PUBLISHER]

We measured low-energy proton radiation induced soft error rates (SER) of standard and reduced-SER (RSER) latches, manufactured in 32 nm and 45 nm bulk CMOS technologies, and conclude that sequential logic elements built in these technologies are not yet susceptible. Further, our results demonstrate that at proton energies where direct ionization dominates, critical charge (Qcrit) plays a far bigger role than at proton energies above the nuclear reaction threshold. [ABSTRACT FROM PUBLISHER]

We investigate the applicability of current total ionizing dose (TID) test protocols in the context of advanced transistor technologies such as Silicon-Germanium heterojunction bipolar transistors (SiGe IIBTs). In SiGe HBTs, an unexpected shift in collector current is observed during total dose irradiation. Using both device and circuit measurements, we investigate this phenomenon and assess its potential importance in hardness as- surance of SiGe components. TCAD simulations were performed to explain the observed current shifts. [ABSTRACT FROM AUTHOR]

Direct ionization from low energy protons is shown to cause upsets in a 65-nm bulk CMOS SRAM, consistent with results reported for other deep submicron technologies. The experimental data are used to calibrate a Monte Carlo rate prediction model, which is used to evaluate the importance of this upset mechanism in typical space environments. For the ISS orbit and a geosynchronous (worst day) orbit, direct ionization from protons is a major contributor to the total error rate, but for a geosynchronous (solar mm) orbit, the proton flux is too low to cause a significant number of events. The implications of these results for hardness assurance are discussed. [ABSTRACT FROM AUTHOR]

Experimental results are presented on single-bit-upsets (SBU) and multiple-bit-upsets (MBU) on a 45 nm SOI SRAM. The accelerated testing results show the SBU-per-bit cross section is relatively constant with technology scaling but the MBU cross section is increasing. The MBU data show the importance of acquiring and analyzing the data with respect to the location of the multiple-bit upsets since the relative location of the cells is important in determining which MBU upsets can be corrected with error correcting code (ECC) circuits. For the SOI SRAMs, a large MBU orientation effect is observed with most of the MBU events occurring along the same SRAM bit-line; allowing ECC circuits to correct most of these MBU events. [ABSTRACT FROM AUTHOR]

The probability of proton-induced multiple-bit upset (MBU) has increased in highly-scaled technologies because device dimensions are small relative to particle event track size. Both proton-induced single event upset (SEU) and MBU responses have been shown to vary with angle and energy for certain technologies. This work analyzes SEU and MBU in a 130 nm CMOS SRAM in which the single-event response shows a strong dependence on the angle of proton incidence. Current proton testing methods do not account for device orientation relative to the proton beam and, subsequently, error rate prediction assumes no angular dependencies. Proton-induced MBU is expected to increase as integrated circuits continue to scale into the deep sub-micron regime. Consequently, the application of current testing methods will lead to an incorrect prediction of error rates. [ABSTRACT FROM AUTHOR]

Abstract: We present the first experimental results confirming the increased SEE sensitivity of SiGe digital bipolar logic circuits operating in a 63MeV proton environment at cryogenic temperatures. A 3× increase in both the error-event and bit-error cross sections is observed as the circuits are cooled from 300K to 77K, with error signature analyses indicating corresponding increases in the average number of bits-in-error and error length over data rates ranging from 50Mbit/s to 4Gbit/s. Single-bit-errors dominate the proton-induced SEU response at both 300K and 77K, as opposed to the multiple-bit-errors seen in the heavy-ion SEU response. Temperature dependent substrate carrier lifetime measurements, when combined with calibrated 2D DESSIS simulations, suggest that the increased transistor charge collection at low temperature is a mobility driven phenomenon. Circuit-level RHBD techniques are shown to be very efficient in mitigating the proton- induced SEU at both 300K and 77K over the data rates tested. These results suggest that the circuit operating temperature must be carefully considered during component qualification for SEE tolerance and indicate the need for broad-beam heavy-ion testing at low temperatures. [Copyright &y& Elsevier]