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This study proposes an implementation based on a low-cost field-programmable gate array (FPGA) of a high-resolution pulse width modulation applied on a single-phase power factor correction (PFC) converter operating with 2 MHz switch frequency. The PFC was implemented using a half-bridge enhancement-mode Gallium Nitride (eGaN) field effect transistor with on-board gate drives (EPC9003 development board) and the MAX10 FPGA.

A single-phase GaN-based bridgeless PFC Boost converter design is proposed regarding multi-domain optimisation concepts. A design guideline describing elements losses are presented concerning the selected power converter topology. Experimental results are also depicted in 750 W power prototype digitally controlled by an FPGA device using switching frequency up to 500 kHz per active switch.

In this paper, a single-phase unity power factor rectifier, based on a hybrid boost converter, resulting from the integration of a conventional dc–dc boost converter and a switched-capacitor voltage doubler is proposed, analysed, designed and tested. The high-power rectifier is controlled by two feedback loops with the same control strategy employed in the conventional boost-based rectifier. The main feature of the proposed rectifier is its ability to output a dc voltage larger than the double of the peak value of the input line voltage, while subjecting the power switches to half of the dc-link voltage, which contributes to reducing the cost and increasing the efficiency. Experimental data were obtained from a laboratory prototype with an input voltage of 220 Vrms, line frequency of 60 Hz, output voltage of 800 Vdc, load power of 1000 W and switching frequency of 50 kHz. The efficiency of the prototype, measured in the laboratory, was 96.5% for full load and 97% for half load.

This paper presents a three-phase multilevel power factor correction (PFC) rectifier employing multistate switching cells. A generalized converter structure is presented based on the connection of switching networks of Vienna-type rectifier topologies through multiinterphase transformers (MIPTs). The resulting rectifier presents the intrinsic benefits to the employed building blocks and the ones added by a modular construction that enables the reduction of passive components and overall losses. The operation of the PFC rectifier is described, including appropriate modulation and control strategies. Design guidelines for the magnetic components are derived for the MIPTs, boost inductors, and power semiconductor devices. Finally, a lab prototype is used to present experimental results. This prototype is rated at 7.5 kW and uses a modular structure to assemble a four legs per phase rectifier. Efficiency above 98% from 40% load and IEC61000-3-2 requirements are observed.

Poly-phase systems have been used for many years in machines and recently in wind power generations. They usually are built by a dual three-phase system, shifted by 30 electrical degrees from each other and with no neutral connection. Typically, this system employs a twelve-pulse diode rectifier to converter ac to dc voltages. However, it may be improved if an active rectifier is used, because it can provide lower distortion in generator currents and regulated output voltage. Taking that into account, this paper proposes a six-phase active rectifier topology for a dual three-phase system. A stationary frame reference for six-phase system is applied to obtain the converter dynamic model in the αβ coordinates and thus a control strategy is proposed in this frame reference. The proposed topology, dynamic model and control strategy were verified by simulation for following specification: 12 kW, 220 V at input voltage and 800 V at the output voltage. The results were appropriated, providing a regulated output voltage, an input current with reduced harmonic distortion and thus high power factor.

Novel simple indirect control concepts for an active power filter (APF) application are proposed here. The concepts are exemplarily presented to control a modified APF structure. The main advantage over other control strategies is the achieved excellent simplicity-to-performance ratio. The proposed control strategies are based on the concept of virtual impedance emulation to provide high power factor in a system. To validate the operating principle, a single-phase low-power prototype has been built and experimentally tested. This prototype operates at a remarkably low switching frequency of 5 kHz and is digitally controlled by a digital signal processor.

This paper proposes a unidirectional step-up rectifier family with high voltage gain. The converters are based on the integration between traditional rectifiers and voltage multiplier switched-capacitor cell. The novel structures are referred to as hybrid boost rectifiers and they provide high gain with low voltage stress on the switches and with low gain in boost stage, which are advantages regarding to design and control. Three new topologies are introduced in this paper, two are bridgeless rectifier, and principle of operation, steady state analysis, dynamic models and simulation results are presented. All topologies provide high power factor in input current and a regulated output voltage.

The single-phase multilevel power-factor correction rectifier employing multistate switching cells is analyzed regarding different operational aspects. The generalization of the number of switching states is performed in order to clarify issues such as the input current ripple, the output currents rms values, power semiconductor stresses, and others. A discussion on the optimal number of switching states is carried out, based on the generated models. In this context, this work is a first step aiming in the efficiency-based optimization of the concept.

Almost two decades of research on unidirectional three-phase multilevel boost-type pulsewidth modulation (PWM) rectifiers have shown the benefits of employing this technology to comply with power quality standards while assuring high efficiency and low volume and weight. However, the unidirectional topologies directly derived from the conventional three-level bidirectional converters, such as the neutral point clamped (NPC), the flying capacitor and the cascaded H-bridge converters have not been properly analyzed. This letter introduces some of the unidirectional topologies that arise from the inspection of the widespread conventional bidirectional converters. Special emphasis is put in the analysis of the NPC-based three-phase/-level PWM rectifier operating as power factor corrector.

This paper proposes a method for calculation of the instantaneous active and reactive power in six-phase system, derived from the Akagi three-phase instantaneous power theory, the proposed method is physical analyzed and the results are validated by simulation.

This paper presents a nonisolated multilevel buck+boost dc-dc converter suitable for high voltage and high power application. It is composed by a Buck-type and a Boost-type converters, both multilevel and bidirectional. The main features of proposed converter are: reduced voltage stress across the semiconductors, allowing its use in high voltage; bidirectional power flow; frequency operation of the inductor is a multiple of the switching frequency, reducing the volume of magnetic component. This paper focuses on the five-level structure of the proposed converter, in which the theoretical analysis is carried out and discussed. In order to validate the theoretical analysis, a prototype with 10 kW output power capability, 1 kV to 750 V input-to-output voltage and 20 kHz of switching frequency was constructed and experimented. The results attest the advantages of the new dc-dc topology and it is reported herein.

Multistate switching cells-based multilevel rectifiers (MLMSR) are a promising technology in power factor correction applications. They are here arranged in a modular structure that is the basis for a Power Electronics Building Block (PEBB). By the implementation of the multi-interphase transformers (MIPT) in a “whiffletree” configuration, multiple cells can be structured in a way that virtually any number of PEBBs can be used to increase a converter rated power. This work presents the conception and development of such a PEBB exemplarily for multi state switching cells multilevel based rectifiers. The proposed PEBB is presented and two lab prototypes are built. Experimental results are presented.

The paper proposes a Lyapunov based approach for assessing the local stability of current self-control strategies for PFC Boost converters subject to load variations. Lyapunov stability conditions are cast in terms of state-dependent linear matrix inequality constraints which are numerically solved via semi-definite solver packages. Numerical simulations and practical experiments are considered to validate the proposed approach.

The one cycle control (OCC) technique has been implemented in power electronics boost converters by analog controllers. In discrete time control system the OCC is rarely used. The main obstacle is the discrete resetable integrator implementation in numeric processor and the limit-cycle caused by discrete-time control system. The digital control in power electronics is a trend, due to various advantages over the analog control. The noise immunity, flexibility in the implementation of control law and parametric invariability are some of many benefits to use digital control. Although, there are some limitations and characteristics should be considered to design the control system. In fact, exactly the inherent discrete-time characteristics are the limitation to implement of OCC technique by digital control. The discrete-time resetable integrator, used in OCC technique, is the main obstacle to experimental implementation. The numeric resolution limitation and consequently duty cycle error can exhibit instability in operation, alike when the converter is lightly loaded. Therefore in this paper, a new approach to implement the discrete-time One Cycle Control PWM modulator is proposed into a single-phase PFC boost converter. The OCC is implemented in FPGA in hardware description language. Simulation results are presented to validate the proposed OCC PWM modulator.

Converters aiming at high power density and efficiency require an optimized design of their constituent components. In this context, the detailed knowledge of the harmonic spectrum generated by the converter is very important in order to design EMC filters and passive components. This work presents a theoretical analysis of the input voltage generated by multi-state switching cells-based single-phase multilevel rectifiers, including its harmonic contents. The proposed study is supported by simulation and experimental results.

This work presents a novel five-level hybrid Half-Bridge/ANPC multilevel inverter. Along with the switching states possibilities, employed modulation techniques, conduction losses analysis, and simulation results from a three-phase topology, it is presented the experimental results from a monophasic structure, operating with 1020Hz switching frequency, output frequency of 60Hz, phase output voltage of 220Vrms, output power of 2.3kW and power factor of 0.92. From the presented results, it can be noticed the reduced losses and better harmonic content.

Normally, one cycle control (OCC) technique is implemented in PFC boost converters by analog controllers and rarely in discrete-time systems. In this paper, a discrete-time OCC PWM modulator is proposed to single-phase PFC boost converter. The discrete-time control system is implemented in FPGA. Simulation and experimental results validate the analyses.

The FPGA device is an IC that can be programmable by software, to implement any logical function. Its inner architecture offers possibility to execute complex algorithms, even some parts running in parallel, improving law control dynamics. In consequence, the FPGA can control power electronics converters successfully. The several segments of the converter control are connected and synchronized by a state machine. Thus, this paper proposes a design of a synchronous state machine to control a PFC boost converter with FPGA. The communication between FPGA and ADC is implemented by SPI communication. The controllers and PWM modulator are build in FPGA to control the converter. Experimental results show the mains signals of state machine and also the boost converter in operation.

This paper shows a comparison between two different control strategies to the bidirectional rectifier with high power factor. The same hardware was applied during the tests for both control techniques and with the controllers implemented on Texas TMS320F2812 DSP. Besides the techniques, this paper will focus on the differences to carry out the controllers and in the results for each applied methodology.

Power quality disturbances, such as voltage sags and instantaneous power interruptions, are probably the most frequent and damaging phenomenon in industrial environments. Thus, to improve the sustainability of electrical equipment, the power supplies should tolerate these disturbances. The PFC boost converter operating in CCM is exhaustively used as a first-stage in the power supplies. The average current mode control is the most popular technique and implemented with analog or discrete-time controllers. However, at instantaneous power interruption, the inner controllers go to saturation mode. Consequently, the switching device (MOSFET), of the converter, might be permanently damage when the power returns after voltage interruption. Another current control technique is self-control. In this case, the dynamics controllers are different. Therefore, this paper investigates the operation of the converter at instantaneous power interruption. The average current mode control and self-control are analyzed. Protection strategy is implemented, by FPGA, in a single-phase CCM PFC boost converter. Simulation and experimental results confirm and validate the analysis.

The single-phase three-level PFC rectifier employing multi-state switching cells is modeled regarding different operational aspects. The generalization of the number of switching states is performed in order to clarify issues such as the input current ripple, the output currents RMS values, semiconductor efforts and others. A discussion on the optimal number of switching states is carried out, based on the generated models. In this context, this work is a first step aiming in the efficiency based optimization of the concept.

Recently, power quality disturbances such as voltage sags and instantaneous power interruptions are, probably, the most frequent and damaging phenomenon in industrial environments. Thus, to improve the sustain-ability of electrical equipment, the power supplies should tolerate these disturbances. The PFC boost converter operating in CCM is exhaustively used as a first-stage in power supplies. The average current mode control is the most popular technique and is usually implemented by IC UC3854. However, at instantaneous power interruption, the inner controllers go to saturation mode. Consequently, the switching device (MOSFET) of the converter might be permanently damage when the power returna after voltage interruption. Another current control technique is self-control. In this case, the dynamics controllers are different. Therefore, this paper investigates the operation of the converter at instantaneous power interruption. The average current mode control and self-control are analyzed. Protection strategy is implemented, by FPGA, in a single-phase CCM PFC boost converter. Simulation and experimental results confirm and validate the analysis.

Risks of energy shortage and control of greenhouse gases emission increase the demand for high efficiency power conversion. Power quality standards require electronic equipment with power factor correction. This adds an extra conversion stage that decreases overall efficiency. Therefore, research on PFC converters with high efficiency is paramount for power conversion equipment. This work proposes new concepts that make use of multilevel topologies and multi-state switching cells in order to improve the efficiency of PWM rectifiers. Analytical and experimental analysis are provided in order to validate this objective.

This paper presents an application control strategy for controlling the input current and DC link voltage of a single-phase voltage-doubler boost PFC (power factor corrector) implemented by FPGA. A sample of the input voltage, or any other current reference, is not necessary, since it is naturally used as reference for the current loop, through the power circuit. The model is more accurate, presenting fewer simplifications and taking better advantage of the natural characteristics of the converter, when compared to classic control, with better results, and many advantages, by simply using a proportional compensator. Some of the advantages of this strategy include greater robustness and simplicity, less susceptibility to noise and a smoother turn-on characteristic. For the voltage loop, although it presents a hyperbolic characteristic, a linearized model was applied, using similar compensator and obtaining even better results than for the classical control strategy. It presents also a natural feedback for the total output voltage and even for the voltage balancing. The FPGA used in the project is an ALTERAreg Cyclone II EP2C35F672C6, presented on the kit DE2, which is a low-cost FPGA with low-consumption at a great speed.

This paper presents a strategy for controlling the input current and output voltages of a single-phase boost PFC (power factor corrector) voltage-doubler, implemented using FPGA. A sample of the input voltage is not necessary, since it is naturally used as reference for the input current, by a natural feedback through the power circuit. This way, the model is more accurate, presenting fewer simplifications and taking better advantage of the natural characteristics of the converter, when compared to classic control, with better results, and many advantages, by simply using a proportional compensator. It also presents superb characteristics for the output voltages control, again with a natural feedback for the total output voltage and even for the voltage balancing, although it's yet necessary an integrator for the total output voltage loop, in order to guarantee the zero steady state error. Despite the hyperbolic characteristic for the voltage model could be a problem, in fact it is very simple to treat, providing yet good characteristics, like the possibility to operate almost without load with a good voltage regulation. Some of the advantages of this strategy include greater robustness and simplicity, emphasizing the output voltage balancing natural feedback, less susceptibility to noise and a smoother turn-on characteristic. The FPGA used in the project is an ALTERAreg Cyclone II EP2C35F672C6, presented on the kit DE2, which is a low-cost FPGA with low-consumption at a great speed.

In this paper the design and experimental results for the isolate unidirectional three-phase buck rectifier are presented. In the previous work this topology was introduced which utilizes a forward/flyback transformer to allow the high-frequency isolation to a three-phase buck rectifier without additional power switches. In order to complement the previously acquired knowledge a review of operation states and modulation, power circuit design and discrete control applied to a prototype are described. Such as, the experimental results to 220 Vrms mains and 2.5 kW at 48 V load with discrete control and unit power factor is presented.

This article presents the study and implementation of a single-phase pre-regulator rectifier with digital control using the FPGA technology. The control technique used aims to obtain power factor correction (PFC) based on average current mode control. The rectifier is a single-phase voltage doubler with a center tap at the voltage output. The FPGA used in the project is an ALTERAreg Cyclone II EP2C35F672C6, present on the kit DE2, which is a low-cost FPGA with low-consumption at a great speed. The output power of prototype implemented was around 500 W.

This paper presents the study and implementation of a single-phase pre-regulator rectifier with digital control using the FPGA technology. The control technique used aims to obtain power factor correction (PFC) based on average current mode control. The rectifier is a single-phase voltage doubler with a center tap at the voltage output. The FPGA used in the project is an ALTERAreg Cyclone II EP2C35F672C6, present on the kit DE2, which is a low-cost FPGA with low-consumption at a great speed. The output power of prototype implemented was around 1000 W. In this project it was just considered the use of the current loop, in other words, just the control of the input current was implemented. The regulation of the output voltages was implemented in another paper using DSP, according to [4].