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In this article, we propose an integrate-and-fire (IF) neuron circuit using a single-gated silicon nanowire feedback field-effect transistor that utilizes a positive feedback loop. The IF operations are investigated through mixed-mode technology computer-aided design simulations. The neuron circuit composed of four component transistors (plus one capacitor) exhibits a high firing frequency of ~20 kHz and low power and energy consumption of 7~μW and 2.9× 10−15 J. The firing frequency and spiking voltage can be controlled through external biasing voltages. Our novel neuron circuit demonstrates a promising potential for use in spiking neural network hardware for very large-scale integration. [ABSTRACT FROM AUTHOR]

We demonstrate the nonvolatile and volatile memory characteristics of a gate-all-around silicon nanowire feedback field-effect transistor (FBFET) with a nitride charge-storage layer analyzed by a commercial TCAD simulator. Our FBFET exhibits a threshold voltage window of 0.76 V with a programming/erasing time of ${1}~\mu \text{s}$ in the nonvolatile memory mode. We investigated the delay of read operations with accumulated charges in the intrinsic channel region in this memory mode. Moreover, the FBFET exhibits a sensing margin of 6.3 $\mu \text{A}$ and a read/write speed of 10 ns with an outstanding retention time, as well as nondestructive read characteristics in the volatile memory mode, allowing this device to operate without any refresh operation. In addition, we describe the operating principle of our device and demonstrate its potential as integrated memory for 3-D integrations. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications. [ABSTRACT FROM AUTHOR]